4f14cd8a39
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
103 lines
2.7 KiB
Plaintext
103 lines
2.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config PLATFORM_USES_FSP1_1
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bool
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select UEFI_2_4_BINDING
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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help
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Does the code require the Intel Firmware Support Package?
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if PLATFORM_USES_FSP1_1
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comment "Intel FSP 1.1"
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config FSP_USE_REPO
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bool "Use FSP binary from 3rdparty/fsp repo"
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select HAVE_FSP_BIN
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depends on SOC_INTEL_BRASWELL && !USE_GOOGLE_FSP
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default y
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config HAVE_FSP_BIN
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bool "Add Intel FSP binary to flash image"
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help
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Select this option to add an Intel FSP binary to
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the resulting coreboot image.
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Note: Without this binary, coreboot builds relying on the FSP
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will not boot
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config FSP_FILE
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string
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prompt "Intel FSP binary path and filename" if !FSP_USE_REPO
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depends on HAVE_FSP_BIN
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default "3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd" if FSP_USE_REPO
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default ""
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help
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The path and filename of the Intel FSP binary for this platform.
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config FSP_LOC
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hex "Intel FSP Binary location in CBFS"
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default 0xfff6e000 if SOC_INTEL_BRASWELL && USE_GOOGLE_FSP
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default 0xfff20000 if SOC_INTEL_BRASWELL
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default 0xffee0000 if SOC_INTEL_SKYLAKE
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help
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The location in CBFS that the FSP is located. This must match the
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value that is set in the FSP binary. If the FSP needs to be moved,
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rebase the FSP with Intel's BCT (tool).
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config DISPLAY_HOBS
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bool "Display hand-off-blocks (HOBs)"
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default n
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config DISPLAY_VBT
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bool "Display Video BIOS Table (VBT)"
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default n
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config DISPLAY_FSP_ENTRY_POINTS
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bool "Display FSP entry points"
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default n
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config DISPLAY_UPD_DATA
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bool "Display UPD data"
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default n
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help
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Display the user specified product data prior to memory
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initialization.
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config USE_GENERIC_FSP_CAR_INC
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bool
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default n
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help
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The chipset can select this to use a generic cache_as_ram.inc file
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that should be good for all FSP based platforms.
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config SKIP_FSP_CAR
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def_bool n
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help
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Selected by platforms that implement their own CAR setup.
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config FSP1_1_DISPLAY_LOGO
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bool "Enable logo"
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default n
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help
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Uses the FSP to display the boot logo. This method supports a
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BMP file only. The uncompressed size can be up to 1 MB.
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config FSP1_1_LOGO_FILE_NAME
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string "Logo file"
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depends on FSP1_1_DISPLAY_LOGO
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp"
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endif #PLATFORM_USES_FSP1_1
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