4fa183fe79
This change renames `struct uart_gpio_pad_config` to `struct uart_controller_config` and adds a new parameter devfn (which expects devfn for the UART controller corresponding to the index in PCI_DEVFN() format). This gets rid of the SoC callback to get `struct device` pointer to the UART controller device. Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49212 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* The sole purpose of this driver is to avoid BAR to be changed during
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* resource allocation. Since configuration space is just 32 bytes it
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* shouldn't cause any fragmentation.
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*/
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#include <console/console.h>
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#include <intelblocks/uart.h>
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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const struct uart_controller_config uart_ctrlr_config[] = {
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#if CONFIG(SOC_INTEL_GEMINILAKE)
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{
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.console_index = 0,
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.devfn = PCH_DEVFN_UART0,
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.gpios = {
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
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},
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},
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{
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.console_index = 2,
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.devfn = PCH_DEVFN_UART2,
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.gpios = {
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART2_TXD */
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},
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},
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#else
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{
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.console_index = 0,
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.devfn = PCH_DEVFN_UART0,
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.gpios = {
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PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */
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PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */
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},
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},
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{
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.console_index = 1,
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.devfn = PCH_DEVFN_UART1,
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.gpios = {
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PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
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PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
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},
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},
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{
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.console_index = 2,
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.devfn = PCH_DEVFN_UART2,
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.gpios = {
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PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
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PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
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},
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},
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#endif
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};
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const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);
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