512b77abb5
This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
33 lines
837 B
C
33 lines
837 B
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/spi.h>
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#include <soc/pci_devs.h>
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int spi_soc_devfn_to_bus(unsigned int devfn)
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{
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switch (devfn) {
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case PCH_DEVFN_SPI:
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return 0;
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case PCH_DEVFN_GSPI0:
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return 1;
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case PCH_DEVFN_GSPI1:
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return 2;
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case PCH_DEVFN_GSPI2:
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return 3;
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}
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return -1;
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}
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