51a57eb5ea
For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
115 lines
3.7 KiB
Plaintext
115 lines
3.7 KiB
Plaintext
chip northbridge/intel/sandybridge
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# IGD Displays
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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# Enable DisplayPort B Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
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register "gpu_panel_power_cycle_delay" = "5" # 400ms
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register "gpu_panel_power_up_delay" = "500" # 50ms
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register "gpu_panel_power_down_delay" = "150" # 15ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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# Set backlight PWM values
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register "gpu_cpu_backlight" = "0x000001d4"
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register "gpu_pch_backlight" = "0x03aa0000"
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register "spd_addresses" = "{0x50, 0, 0x52, 0}"
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register "ec_present" = "1"
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# FIXME: Native raminit requires reduced max clock
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register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
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register "usb_port_config" = "{
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{ 0, 3, 0x0000 },
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{ 1, 0, 0x0040 },
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{ 1, 1, 0x0040 },
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{ 1, 1, 0x0040 },
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{ 0, 3, 0x0000 },
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{ 0, 3, 0x0000 },
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{ 0, 3, 0x0000 },
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{ 0, 3, 0x0000 },
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{ 1, 4, 0x0040 },
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{ 0, 4, 0x0000 },
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{ 1, 4, 0x0040 },
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{ 0, 4, 0x0000 },
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{ 0, 4, 0x0000 },
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{ 0, 4, 0x0000 },}"
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device domain 0 on
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device ref host_bridge on end # host bridge
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device ref igd on end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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# Set Lid Switch to SMI to capture in recovery mode. It gets reset to
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# SCI mode when we go to ACPI mode.
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register "alt_gp_smi_en" = "0x8100"
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register "gpi7_routing" = "2"
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register "gpi8_routing" = "1"
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register "gpi15_routing" = "1" #lid switch gpe
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register "sata_port_map" = "0x1"
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register "usb_port_config" = "{
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{0, 0, -1}, /* P0: Empty */
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{1, 0, 0}, /* P1: Left USB 1 (OC0) */
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{1, 0, 1}, /* P2: Left USB 2 (OC1) */
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{1, 0, 1}, /* P3: Left USB 3 (OC1) */
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{0, 0, -1}, /* P4-P7: Empty */
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{0, 0, -1},
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{0, 0, -1},
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{0, 0, -1},
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/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
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{1, 0, -1}, /* P8: MiniPCIe (WLAN) (no OC) */
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{0, 0, -1}, /* P9: Empty */
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{1, 0, -1}, /* P10: Camera (no OC) */
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{0, 0, -1}, {0, 0, -1}, {0, 0, -1}
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}"
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# EC range is 0xFD60 (EC_IO) and 0x68/0x6C
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register "gen1_dec" = "0x0004fd61"
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register "gen2_dec" = "0x00040069"
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "true"
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device ref mei1 on end # Management Engine Interface 1
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device ref mei2 off end # Management Engine Interface 2
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device ref me_ide_r off end # Management Engine IDE-R
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device ref me_kt off end # Management Engine KT
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device ref gbe off end # Intel Gigabit Ethernet
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device ref ehci2 on end # USB2 EHCI #2
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device ref hda on end # High Definition Audio
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device ref pcie_rp1 off end # PCIe Port #1
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device ref pcie_rp2 on end # PCIe Port #2 (WLAN)
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device ref pcie_rp3 on end # PCIe Port #3 (ETH0)
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device ref pcie_rp4 off end # PCIe Port #4
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device ref pcie_rp5 off end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref ehci1 on end # USB2 EHCI #1
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device ref pci_bridge off end # PCI bridge
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device ref lpc on
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chip ec/compal/ene932
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# 60/64 KBC
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC bridge
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device ref sata1 on end # SATA Controller 1
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device ref smbus on
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subsystemid 0x18D1 0x04B4
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end # SMBus
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device ref sata2 off end # SATA Controller 2
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device ref thermal on end # Thermal
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end
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end
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end
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