5268b76801
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
515 lines
17 KiB
C
515 lines
17 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <soc/ddr_init.h>
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#include <soc/ddr_private_reg.h>
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/*
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* Configuration for the Winbond W631GG6KB part using
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* Synopsys DDR uMCTL and DDR Phy
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*/
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int init_ddr3(void)
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{
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uint32_t temp_rw_val;
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temp_rw_val = read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
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/* Set CLK_EN = 1 */
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temp_rw_val |= 0x2;
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write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val);
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read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
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/*
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* Reset the AXI bridge and DDR Controller in case any spurious
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* writes have already happened to DDR
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*/
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/* Drive the 3 resets low */
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write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002);
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read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
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read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
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/* And release */
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write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F);
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/* Dummy read to fence the access between the reset above and
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* the DDR controller writes below
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*/
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read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
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/* Timings for 400MHz
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* therefore 200MHz (5ns) uMCTL (Internal) Rate
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*/
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/* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */
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write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8);
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/* TINIT: t_init Timing Register: at least 200us 200h C8h */
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write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8);
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/* TRSTH: Reset High Time Register DDR3 ONLY */
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write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4);
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/* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/
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write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014);
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/* DTUAWDT DTU Address Width Register
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* 1:0 column_addr_width Def 10 - 7 3 10 bits
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* 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank)
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* 7:6 row_addr_width Def 14 - 13 1 3 bits
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* 10:9 number_ranks Def 1 - 1 0 0 1 Rank
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*/
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write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B);
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/* MCFG
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* 0 BL 1 -> 8 fixed
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* 1 RDRIMM 0
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* 2 BL8 Burst Terminate 0
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* 3 2T = 0
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* 4 Multi Rank 0
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* 5 DDR3 En 1
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* 6 LPDDR S4 En
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* 7 BST En 0, 1 for LPDDR2/3
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* 15:8 Power down Idle, passed by argument
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* 16 Power Down Type, passed by argument
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* 17 Power Down Exit 0 = slow, 1 = fast, pba
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* 19:18 tFAW 45ns = 9 clk 5*2 -1 1h
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* 21:20 mDDR/LPDDR2 BL 0
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* 23:22 mDDR/LPDDR2 Enable 0
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* 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0
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*/
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write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021);
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/* MCFG1: Memory Configuration-1 Register
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* c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB
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* 10:8 Fine tune MCFG.19:18 -1
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* 15:11 Reserved
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* 23:16 Hardware Idle Period NA 0
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* 30:24 Reserved
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* 31 c_active_in_pin exit auto clk stop NA 0
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*/
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write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100);
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/* DCR DRAM Config
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* 2:0 SDRAM => DDR3 3
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* 3 DDR 8 Bank 1
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* 6:4 Primary DQ DDR3 Only 0
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* 7 Multi-Purpose Register DDR3 Only 0
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* 9:8 DDRTYPE LPDDR2 00
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* 26:10 Reserved
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* 27 NOSRA No Simultaneous Rank Access 0
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* 28 DDR 2T 0
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* 29 UDIMM NA 0
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* 30 RDIMM NA 0
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* 31 TPD LPDDR2 0
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*/
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write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B);
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/* Generate to use with PHY and PCTL
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* MR0 : DDR3 mode register 0
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* 1:0 BL 8 fixed 00
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* 3 BT Sequential 0 Interleaved 1 = 0
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* 6:4,2 CL 6
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* 7 TM Normal 0
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* 8 DLL Reset 1 (self Clearing)
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* 11:9 WR 15 ns 6 (010)
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* 12 PD Slow 1 Fast 0 0
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* 15:13 RSVD RSVD
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* 31:16 Reserved
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*/
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write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
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/* MR1 : DDR3 mode register 1
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* Generate to use with PHY and PCTL
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* 0 DE DLL Enable 0 Disable 1
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* 5,1 DIC Output Driver RZQ/6
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* 9,6,2 ODT RZQ/4
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* 4:3 AL = 0
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* 7 write leveling enabled 0
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* 10 DQS 0 diff, 1 single = 0
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* 11 TDQS NA 0
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* 12 QOFF Normal mode 0
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* 15:13 RSVD
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* 31:16 Reserved
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*/
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write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004);
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/* MR2 : DDR3 mode register 2
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* Generate to use with PHY and PCTL
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* 2:0 PASR, NA 000
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* 3 CWL 000 (5) tck = 22.5ns
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* 6 auto self-refresh 1
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* 7 SRT normal 0
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* 8 RSVD
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* 10:9 dynamic ODT 10 RZQ/2
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* 31:11 Reserved
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*/
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write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440);
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/* MR3: DDR3 mode register 3
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* 1:0 MPRLOC 00
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* 2 MPR 0
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*/
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write32(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000);
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/* DTAR : Data Training Register
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* 11:0 Data Training Column Address
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* 27:12 Data Training Row Address
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* 30:28 Data Training Bank Address
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* 31 Data Training Use MPR (DDR3 Only)
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*/
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write32(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000);
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/* DSGCR
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* 0 PUREN Def 1
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* 1 BDISEN Def 1
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* 2 ZUEN Def 1
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* 3 LPIOPD DEf 1 0
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* 4 LPDLLPD DEf 1 0
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* 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys
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* 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys
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* 11 NOBUB No Bubbles, adds latency 1
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* 12 FXDLAT Fixed Read Latency 0
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* 15:13 Reserved
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* 19:16 CKEPDD CKE Power Down 0000
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* 23:20 ODTPDD ODT Power Down 0000
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* 24 NL2PD Power Down Non LPDDR2 pins 0
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* 25 NL2OE Output Enable Non LPDDR2 pins 1
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* 26 TPDPD LPDDR Only 0
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* 27 TPDOE LPDDR Only 1
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* 28 CKOE Output Enable Clk's 1
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* 29 ODTOE Output Enable ODT 1
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* 30 RSTOE RST# Output Enable 1
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* 31 CKEOE CKE Output Enable 1
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*/
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write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927);
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/* Sysnopsys advised 500R pullup/pulldown DQS DQSN */
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write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40);
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/* DTPR0 : DRAM Timing Params 0
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* 1:0 tMRD 0
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* 4:2 tRTP 2
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* 7:5 tWTR 4
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* 11:8 tRP 6
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* 15:12 tRCD 6
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* 20:16 tRAS 15
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* 24:21 tRRD 4 for x16
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* 30:25 tRC 21
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* 31 tCCD 0 BL/2 Cas to Cas
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*/
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write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688);
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/* DTPR1 : DRAM Timing Params 1
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* 1:0 ODT On/Off Del Std 0
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* 2 tRTW Rd2Wr Del 0 std 1 +1 0
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* 8:3 tFAW 20 Clk
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* 10:9 tMOD DDR3 Only 15
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* 11 tRTODT DDR3 Only 0
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* 15:12 Reserved
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* 23:16 tRFC 160ns 64 ref 131
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* 26:24 tDQSCK LPDDR2 only 1
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* 29:27 tDQSCKmax 1
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* 31:30 Reserved
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*/
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write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0);
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/* DTPR2 : DRAM Timing Params 2
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* 9:0 tXS exit SR def 512d
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* 14:10 tXP PD Exit Del 8 5
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* 18:15 tCKE CKE Min pulse 5
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* 28:19 tDLLK DLL Lock time 512d
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* 32:29 Reserved
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*/
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write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600);
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/* PTR0 : PHY Timing Params 0
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* 5:0 tDLLRST Def 27
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* 17:6 tDLLLOCK Def 2750
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* 21:18 tITMSRST Def 8
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* 31:22 Reserved 0
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*/
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write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B);
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/* PTR1 : PHY Timing Params 1
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* 18:0 : tDINITO DRAM Init time 500us 200,000 Dec 0x30D40
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* 29:19 : tDINIT1 DRAM Init time tRFC + 10ns 68
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*/
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write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40);
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/* DQS gating configuration: passive windowing mode */
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/*
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* PGCR: PHY General cofiguration register
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* 0 ITM DDR mode: 0
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* 1 DQS gading configuration: passive windowing 1
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* 2 DQS drift compensation: not supported in passive windowing 0
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* 4:3 DQS drift limit 0
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* 8:5 Digital test output select 0
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* 11:9 CK Enable: one bit for each 3 CK pair: 0x7
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* 13:12 CK Disable values: 0x2
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* 14 CK Invert 0
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* 15 IO loopback 0
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* 17:16 I/O DDR mode 0
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* 21:18 Ranks enable by training: 0xF
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* 23:22 Impedance clock divider select 0x2
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* 24 Power down disable 1
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* 28:25 Refresh during training 0
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* 29 loopback DQS shift 0
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* 30 loopback DQS gating 0
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* 31 loopback mode 0
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*/
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write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02);
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/* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */
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if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007))
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return DDR_TIMEOUT;
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/* PIR : PHY controlled init */
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write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F);
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/* PGSR : Wait for DRAM Init Done */
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if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007))
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return DDR_TIMEOUT;
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/* PIR : controller DRAM initialization */
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write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001);
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/* PGSR : Wait for DRAM Init Done */
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if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000000F))
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return DDR_TIMEOUT;
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/********************************************************************/
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/* DF1STAT0 : wait for DFI_INIT_COMPLETE */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET,
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0x00000001))
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return DDR_TIMEOUT;
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/* POWCTL : Start the memory Power Up seq*/
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write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001);
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/* POWSTAT : wait for POWER_UP_DONE */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET,
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0x00000001))
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return DDR_TIMEOUT;
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/*
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* TREFI : t_refi Timing Register 1X
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* 12:0 t_refi 7.8us in 100ns 0x4E
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* 15:13 Reserved 0
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* 18:16 num_add_ref 0
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* 30:19 Reserved 0
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* 31 Update 1
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*/
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write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E);
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/* TMRD : t_mrd Timing Register -- Range 2 to 4*/
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write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004);
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/*
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* TRFC : t_rfc Timing Register -- Range 15 to 131
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* 195ns / 2.5ns 78 x4E
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*/
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write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E);
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/* TRP : t_rp Timing Register -- Range 3 to 7
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* 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6
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* 17:16 rpea_extra DDR3 - value 0
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*/
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write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006);
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/* TAL : Additive Latency Register -- AL in MR1 */
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write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000);
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/* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */
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write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006);
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/* TCWL : CAS Write Latency Register --CASL-1 */
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write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
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/* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */
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write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);
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/* TRC : Min. ROW cycle time 21
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* 57.5ns / 2.5ns = 23d Playing safe 24
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*/
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write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);
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/* TRCD : Row to Column Delay # Range 3 to 7 (TCL = TRCD)
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* 12.5ns / 2.5ns = 5 but running 6-6-6 6
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*/
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write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006);
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/* TRRD : Row to Row delay -- Range 2 to 6
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* 2K Page 10ns / 2.5ns = 4
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*/
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write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004);
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/* TRTP : Read to Precharge time -- Range 2 to 4
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* Largest 4 or 7.5ns / 2.5ns = 4
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*/
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write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004);
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/* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 */
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write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006);
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/* TWTR : Write to read turn around time -- Range 2 to 4
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* Largest 4 or 7.5ns / 2.5ns = 4
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*/
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write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004);
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/* TEXSR : Exit Self Refresh to first valid cmd: tXS 512 */
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write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200);
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/* TXP : Exit Power Down to first valid cmd
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* tXP 2, Settingto 3 to match PHY
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*/
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write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003);
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/* TDQS : t_dqs Timing Register
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* DQS additional turn around Rank 2 Rank (1 Rank) Def 1
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*/
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write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001);
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/* TRTW : Read to Write turn around time Def 3
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* Actual gap t_bl + t_rtw
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*/
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write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003);
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/* TCKE : CKE min pulse width DEf 3 */
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write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003);
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/* TXPDLL : Slow Exit Power Down to first valid cmd delay
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* tXARDS 10+AL = 10
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*/
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write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A);
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/* TCKESR : Min CKE Low width for Self refresh entry to exit
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* t_ckesr = 0 DDR2
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*/
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write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004);
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/* TMOD : MRS to any Non-MRS command -- Range 0 to 31 */
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write32(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F);
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/* TZQCS : SDRAM ZQ Calibration Short Period */
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write32(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040);
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/* TZQCL : SDRAM ZQ Calibration Long Period */
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write32(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200);
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/* SCFG : State Configuration Register (Enabling Self Refresh)
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* 0 LP_en Leave Off for Bring Up 0
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* 5:1 Reserved
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* 6 Synopsys Internal Only 0
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* 7 Enale PHY indication of LP Opportunity 1
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* 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4
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* 16:12 Additional delay on accertion of ac_pdd 4
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* 31:17 Reserved
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*/
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write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480);
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/* TREFI_MEM_DDR3 */
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write32(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30);
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/* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */
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write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002);
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/* DFITRDDATAEN : Read cmd to dfi_rddata_en */
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write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002);
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/*
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* DFITPHYWRDATA : dfi_wrdata_en to drive wr data
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* DFI Clks wrdata_en to wrdata Def 1
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*/
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write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000);
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/*
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* DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid
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* DFI clks max rddata_en to rddata_valid Def 15
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*/
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write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008);
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/* DFISTCFG0 : Drive various DFI signals appropriately
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* 0 dfi_init_start 1
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* 1 dfi_freq_ratio_en 1
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* 2 dfi_data_byte_disable_en 1
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*/
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write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007);
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/* DFISTCFG1 : Enable various DFI support
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* 0 dfi_dram_clk_disable_en 1
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* 1 dfi_dram_clk_disable_en_pdp only lPDDR 0
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*/
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write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001);
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/* DFISTCFG2 : Enable Parity and asoc interrupt
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* 0 dfi_parity_in Enable 1
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* 1 Interrupt on dfi_parity_error 1
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*/
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write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003);
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/* DFILPCFG0 : DFI Low Power Interface Configuration
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* 0 Enable DFI LP IF during PD 1
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* 3:1 Reserved
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* 7:4 DFI tlp_wakeup time 0
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* 8 Enable DFI LP IF during SR 1
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* 11:9 Reserved
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* 15:12 dfi_lp_wakeup in SR 0
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* 19:16 tlp_resp DFI 2.1 recomend 7
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* 23:20 Reserved
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* 24 Enable DFI LP in Deep Power Down 0
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* 27:25 Reserved
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* 31:28 DFI LP Deep Power Down Value 0
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*/
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write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101);
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/* DFIODTCFG : DFI ODT Configuration
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* Only Enabled on Rank0 Writes
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* 0 rank0_odt_read_nsel 0
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* 1 rank0_odt_read_sel 0
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* 2 rank0_odt_write_nsel 0
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* 3 rank0_odt_write_sel 1
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*/
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write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008);
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/* DFIODTCFG1 : DFI ODT Configuration
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* 4:0 odt_lat_w 0
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* 12:8 odt_lat_r 0 Def
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* 4:0 odt_len_bl8_w 6 Def
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* 12:8 odt_len_bl8_r 6 Def
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*/
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write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);
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/* Memory initialization */
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/* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
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* 3:0 cmd_opcode PREA 00001
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* 16:4 cmd_addr 0
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* 19:17 bank_addr 0
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* 23:20 rank_sel 0 0001
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* 27:24 cmddelay 0
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* 30:24 Reserved
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*/
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/* MCMD: MR2 */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00004403))
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return DDR_TIMEOUT;
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/* MCMD: MR3 */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000003))
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return DDR_TIMEOUT;
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/* MCMD: MR1 */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000043))
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return DDR_TIMEOUT;
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/* MCMD: MR0 */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00015203))
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return DDR_TIMEOUT;
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/* MCMD: ZQS cmd, long 5 short 4 */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00104005))
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return DDR_TIMEOUT;
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/* MCMD: deselect command */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100000))
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return DDR_TIMEOUT;
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/* MCMD: deselect command */
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write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A);
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/* MRS cmd wait for completion */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x0010000A))
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return DDR_TIMEOUT;
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/* DCFG : DRAM Density 256 Mb 16 Bit IO Width
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* 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2
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* 5:2 Density 2Gb = 5
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* 6 Dram Type (MDDR/LPDDR2) Only 0
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* 7 Reserved 0
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* 10:8 Address Map R/B/C = 1
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* 31:11 Reserved
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*/
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write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
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/* PCFG_0 : Port 0 AXI config */
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write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);
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/* SCTL : UPCTL switch INIT CONFIG State */
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write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001);
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/* STAT : Wait for Switch INIT to Config State */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001))
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return DDR_TIMEOUT;
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/* STAT : Wait for Switch INIT to Config State */
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write32(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001);
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/* STAT : Wait for Switch INIT to Config State */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_CMDTSTAT_OFFSET,
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0x00000001))
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return DDR_TIMEOUT;
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/* Use PHY for DRAM init */
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write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181);
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/* STAT : Wait for Switch INIT to Config State */
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if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F))
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return DDR_TIMEOUT;
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/* Disable Impedance Calibration */
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write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A);
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write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A);
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/* SCTL : UPCTL switch Config to ACCESS State */
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write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002);
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/* STAT : Wait for switch CFG -> GO State */
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if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3))
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return DDR_TIMEOUT;
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return 0;
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}
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