5391e554e1
Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
135 lines
4.3 KiB
C
135 lines
4.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/early_variables.h>
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#include <boot_device.h>
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#include <cbfs.h>
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#include <commonlib/region.h>
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#include <console/console.h>
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#include <fmap.h>
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#include <intelblocks/fast_spi.h>
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/*
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* BIOS region on the flash is mapped right below 4GiB in the address
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* space. However, 256KiB right below 4GiB is decoded by read-only SRAM and not
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* boot media.
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*
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* +-----------+ 0
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* | |
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* +--------+ | |
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* | IFD | | |
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* bios_start +---> +--------+------------------> +-----------+ 4GiB - bios_size
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* ^ | | ^ | |
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* | | | | | |
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* | | | bios_mapped_size | BIOS |
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* | | BIOS | | | |
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* bios_size | | | | |
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* | | | v | |
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* | | +------------------> +-----------+ 4GiB - 256KiB
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* | | | | Read only |
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* v | | | SRAM |
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* bios_end +---> +--------+ +-----------+ 4GiB
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* | Device |
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* | ext |
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* +--------+
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*
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*/
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static size_t bios_size CAR_GLOBAL;
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static struct mem_region_device shadow_dev CAR_GLOBAL;
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static struct xlate_region_device real_dev CAR_GLOBAL;
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static void bios_mmap_init(void)
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{
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size_t size, start, bios_mapped_size;
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uintptr_t base;
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size = car_get_var(bios_size);
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/* If bios_size is initialized, then bail out. */
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if (size != 0)
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return;
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start = fast_spi_get_bios_region(&size);
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/* BIOS region is mapped right below 4G. */
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base = 4ULL * GiB - size;
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/*
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* The 256 KiB right below 4G are decoded by readonly SRAM,
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* not boot media.
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*/
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bios_mapped_size = size - 256 * KiB;
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struct mem_region_device *shadow_dev_ptr;
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struct xlate_region_device *real_dev_ptr;
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shadow_dev_ptr = car_get_var_ptr(&shadow_dev);
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real_dev_ptr = car_get_var_ptr(&real_dev);
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mem_region_device_ro_init(shadow_dev_ptr, (void *)base,
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bios_mapped_size);
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xlate_region_device_ro_init(real_dev_ptr, &shadow_dev_ptr->rdev,
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start, bios_mapped_size,
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CONFIG_ROM_SIZE);
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car_set_var(bios_size, size);
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}
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const struct region_device *boot_device_ro(void)
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{
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bios_mmap_init();
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struct xlate_region_device *real_dev_ptr;
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real_dev_ptr = car_get_var_ptr(&real_dev);
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return &real_dev_ptr->rdev;
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}
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static int iafw_boot_region_properties(struct cbfs_props *props)
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{
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struct region regn;
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/* use fmap to locate CBFS area */
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if (fmap_locate_area("COREBOOT", ®n))
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return -1;
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props->offset = region_offset(®n);
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props->size = region_sz(®n);
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printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size);
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return 0;
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}
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/*
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* Named cbfs_master_header_locator so that it overrides the default, but
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* incompatible locator in cbfs.c
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*/
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const struct cbfs_locator cbfs_master_header_locator = {
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.name = "IAFW Locator",
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.locate = iafw_boot_region_properties,
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};
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