53be14c9e2
Change-Id: Ie9c3ef9fb4b3b2a0450a56e1d752b6509fa72a86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10364 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Stefan Reinauer <stefan.reinauer@coreboot.org>
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* Copyright (C) 2010 Kevin O'Connor <kevin@koconnor.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <pc80/keyboard.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <drivers/intel/gma/i915.h>
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#define Q35_PAM0 0x90
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static const unsigned char qemu_q35_irqs[] = {
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10, 10, 11, 11,
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10, 10, 11, 11,
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};
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struct i915_gpu_controller_info gfx_controller_info = {
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.ndid = 3,
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.did = {
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0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005
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}
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};
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const struct i915_gpu_controller_info *
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intel_gma_get_controller_info(void)
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{
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return &gfx_controller_info;
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}
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static void qemu_nb_init(device_t dev)
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{
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/* Map memory at 0xc0000 - 0xfffff */
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int i;
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uint8_t v = pci_read_config8(dev, Q35_PAM0);
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v |= 0x30;
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pci_write_config8(dev, Q35_PAM0, v);
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pci_write_config8(dev, Q35_PAM0 + 1, 0x33);
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pci_write_config8(dev, Q35_PAM0 + 2, 0x33);
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pci_write_config8(dev, Q35_PAM0 + 3, 0x33);
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pci_write_config8(dev, Q35_PAM0 + 4, 0x33);
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pci_write_config8(dev, Q35_PAM0 + 5, 0x33);
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pci_write_config8(dev, Q35_PAM0 + 6, 0x33);
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/* This sneaked in here, because Qemu does not
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* emulate a SuperIO chip
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*/
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pc_keyboard_init();
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/* setup IRQ routing for pci slots */
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for (i = 0; i < 25; i++)
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pci_assign_irqs(0, i, qemu_q35_irqs + (i % 4));
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/* setup IRQ routing southbridge devices */
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for (i = 25; i < 32; i++)
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pci_assign_irqs(0, i, qemu_q35_irqs);
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}
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static void qemu_nb_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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/* reserve mmconfig */
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fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10,
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IORESOURCE_RESERVE);
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}
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static struct device_operations nb_operations = {
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.read_resources = qemu_nb_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = qemu_nb_init,
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.ops_pci = 0,
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};
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static const struct pci_driver nb_driver __pci_driver = {
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.ops = &nb_operations,
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.vendor = 0x8086,
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.device = 0x29c0,
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};
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