544878b563
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
81 lines
2.3 KiB
C
81 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Keith Hui <buurin@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/cpu.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include "i440bx.h"
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void *cbmem_top(void)
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{
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/* Base of TSEG is top of usable DRAM */
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/*
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* SMRAM - System Management RAM Control Register
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* 0x72
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* [7:4] Not relevant to this function.
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* [3:3] Global SMRAM Enable (G_SMRAME)
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* [2:0] Hardwired to 010.
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*
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* ESMRAMC - Extended System Management RAM Control
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* 0x73
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* [7:7] H_SMRAM_EN
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* 1 = When G_SMRAME=1, High SMRAM space is enabled at
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* 0x100A0000-0x100FFFFF and forwarded to DRAM address
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* 0x000A0000-0x000FFFFF.
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* 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at
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* 0x000A0000-0x000BFFFF.
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* [6:3] Not relevant to this function.
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* [2:1] TSEG Size (T_SZ)
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* Selects the size of the TSEG memory block, if enabled.
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* 00 = 128KiB
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* 01 = 256KiB
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* 10 = 512KiB
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* 11 = 1MiB
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* [0:0] TSEG_EN
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* When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to
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* appear between DRAM address (TOM-<TSEG Size>) to TOM.
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*
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* Source: 440BX datasheet, pages 3-28 thru 3-29.
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*/
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unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB;
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int gsmrame = pci_read_config8(NB, SMRAM) & 0x8;
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/* T_SZ and TSEG_EN */
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int tseg = pci_read_config8(NB, ESMRAMC) & 0x7;
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if ((tseg & 0x1) && gsmrame) {
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int tseg_size = 128 * KiB * (1 << (tseg >> 1));
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tom -= tseg_size;
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}
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return (void *)tom;
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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}
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