5449007425
* Add support for the SuperIO part of IT8528E * Based on the IT8528E datasheet and tests on vendor firmware TODO: Add support for accessing EC space, which should be implemented in src/ec/ instead, as it's a separate logical unit. No datasheet is publicy available. Tested on wedge100s. The serial works under the OS without CONFIG_CONSOLE_SERIAL. Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
74 lines
2.7 KiB
C
74 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
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* Copyright (C) 2017 Gergely Kiss <mail.gery@gmail.com>
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* Copyright (C) 2019 9Elements GmbH <patrick.rudolph@9elements.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pnp.h>
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#include <arch/io.h>
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#include <stdlib.h>
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#include <superio/conf_mode.h>
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#include "it8528e.h"
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static void it8528e_init(struct device *dev)
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{
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = it8528e_init,
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.ops_pnp_mode = &pnp_conf_mode_870155_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
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{ NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
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{ NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
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{ NULL, IT8528E_KBCM, PNP_IRQ0, },
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/* Documentation: Program io0 = 0x60 and io1 = 0x64 */
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{ NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
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{ NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
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{ NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, },
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/* Documentation: Program io0 = 0x70 and io1 = 0x272 */
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{ NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
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0xfffe, 0xfffe, 0xfffe, 0xfffe},
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/* Documentation: Program io0 = 0x62 and io1 = 0x66 */
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{ NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
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{ NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, 0x07fc,
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0x07fc, 0xfff0 },
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/* Documentation is unclear if PMC3-5 have LPC I/O decoding support */
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{ NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
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{ NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
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{ NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
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{ NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
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{ NULL, IT8528E_PECI, PNP_IO0, 0xfff8 },
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_ite_it8528e_ops = {
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CHIP_NAME("ITE IT8528E Super I/O")
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.enable_dev = enable_dev,
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};
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