55009af42c
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <assert.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/cpu.h>
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#include <soc/secure_boot.h>
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static void enable_core_clocks(int cpu)
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{
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const uint32_t cpu_clocks[] = {
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[0] = CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_DBG0 |
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CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CX0,
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[1] = CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_DBG1 |
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CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CX1,
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[2] = CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_DBG2 |
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CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CX2,
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[3] = CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG3 |
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CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX3,
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};
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assert (cpu < CONFIG_MAX_CPUS);
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/* Clear reset of CPU components. */
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write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu_clocks[cpu]);
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}
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void cpu_prepare_startup(void *entry_64)
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{
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struct tegra_secure_boot *sb =
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(struct tegra_secure_boot *)TEGRA_SB_BASE;
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/*
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* T210 TRM, section 12.4.4.2: "SB_AA64_RESET_LOW_0[0:0] is used to
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* decide between CPU boot up in AARCH32 (=0) or AARCH64 (=1) mode.
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* This bit .. is sampled only during 'cold reset of CPU'. Before the
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* CPU is powered up, the CPU reset vector is loaded in
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* EVP_CPU_REST_VECTOR_0 for 32-bit boot mode .... However, the CPU
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* decides to boot in 32-/64-bit mode based on
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* SB_AA64_RESET_LOW_0[0:0]. If this bit is set (=1), the CPU boots in
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* 64-bit mode using SB_AA64_RESET_* as the reset address. If this bit
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* is clear (=0), CPU boots in 32-bit mode using EVP_CPU_RESET_VECTOR."
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*/
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write32(&sb->sb_aa64_reset_low, (uintptr_t)entry_64);
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setbits32(&sb->sb_aa64_reset_low, 1);
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write32(&sb->sb_aa64_reset_high, 0);
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}
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void start_cpu_silent(int cpu, void *entry_64)
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{
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cpu_prepare_startup(entry_64);
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enable_core_clocks(cpu);
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}
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void start_cpu(int cpu, void *entry_64)
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{
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printk(BIOS_DEBUG, "Starting CPU%d @ %p.\n", cpu, entry_64);
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start_cpu_silent(cpu, entry_64);
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}
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