55009af42c
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Qualcomm Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <types.h>
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#include <gpio.h>
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void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
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uint32_t drive_str, uint32_t enable)
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{
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uint32_t reg_val;
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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/* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */
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assert(pull <= GPIO_PULL_UP);
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reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) |
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((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |
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((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |
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((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);
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write32(®s->cfg, reg_val);
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}
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void gpio_set(gpio_t gpio, int value)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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write32(®s->in_out, (!!value) << GPIO_IO_OUT_SHFT);
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}
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int gpio_get(gpio_t gpio)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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return ((read32(®s->in_out) >> GPIO_IO_IN_SHFT) &
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GPIO_IO_IN_BMSK);
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}
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void gpio_input_pulldown(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT_DISABLE);
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}
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void gpio_input_pullup(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT_DISABLE);
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}
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void gpio_input(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_DISABLE);
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}
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void gpio_output(gpio_t gpio, int value)
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{
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gpio_set(gpio, value);
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE);
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}
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void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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pull, GPIO_2MA, GPIO_OUTPUT_DISABLE);
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clrsetbits32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
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GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT);
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clrsetbits32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
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<< GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE
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<< GPIO_INTR_RAW_STATUS_EN_SHIFT);
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}
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int gpio_irq_status(gpio_t gpio)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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if (!(read32(®s->intr_status) & GPIO_INTR_STATUS_MASK))
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return 0;
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write32(®s->intr_status, GPIO_INTR_STATUS_DISABLE);
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return 1;
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}
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