55437c57a9
SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
127 lines
3.3 KiB
Plaintext
127 lines
3.3 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Advanced Micro Devices, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config SOUTHBRIDGE_AMD_CIMX_SB800
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bool
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default n
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select IOAPIC
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select AMD_SB_CIMX
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if SOUTHBRIDGE_AMD_CIMX_SB800
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/amd/cimx/sb800/bootblock.c"
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config ENABLE_IDE_COMBINED_MODE
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bool "Enable SATA IDE combined mode"
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default n
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help
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If Combined Mode is enabled. IDE controller is exposed and
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SATA controller has control over Port0 through Port3,
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IDE controller has control over Port4 and Port5.
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If Combined Mode is disabled, IDE controller is hidden and
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SATA controller has full control of all 6 Ports when operating in non-IDE mode.
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config IDE_COMBINED_MODE
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hex
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default "0x0" if ENABLE_IDE_COMBINED_MODE
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default "0x1" if !ENABLE_IDE_COMBINED_MODE
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choice
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prompt "SATA Mode"
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default SB800_SATA_IDE
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help
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Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
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The default is NATIVE.
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config SB800_SATA_IDE
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bool "NATIVE"
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help
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NATIVE is the default mode and does not require a ROM.
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config SB800_SATA_AHCI
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bool "AHCI"
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help
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AHCI may work with or without AHCI ROM. It depends on the payload support.
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For example, seabios does not require the AHCI ROM.
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config SB800_SATA_RAID
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bool "RAID"
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help
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sb800 RAID mode must have the two required ROM files.
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endchoice
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config SB800_SATA_MODE
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hex
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depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
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default "0x0" if SB800_SATA_IDE
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default "0x1" if SB800_SATA_RAID
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default "0x2" if SB800_SATA_AHCI
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config SB_SUPERIO_HWM
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bool
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default n
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if SB800_SATA_AHCI
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config AHCI_ROM_ID
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string "AHCI device PCI IDs"
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default "1002,4391"
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config SB800_AHCI_ROM
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bool "Add a AHCI ROM"
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config AHCI_ROM_FILE
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string "AHCI ROM path and filename"
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depends on SB800_AHCI_ROM
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default "site-local/sb800/ahci.bin"
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endif
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if SB800_SATA_RAID
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config RAID_ROM_ID
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string "RAID device PCI IDs"
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default "1002,4393"
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help
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1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
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config RAID_ROM_FILE
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string "RAID ROM path and filename"
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depends on SB800_SATA_RAID
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default "site-local/sb800/raid.bin"
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config RAID_MISC_ROM_FILE
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string "RAID Misc ROM path and filename"
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default "site-local/sb800/misc.bin"
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depends on SB800_SATA_RAID
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config RAID_MISC_ROM_POSITION
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hex "RAID Misc ROM Position"
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default 0xFFF00000
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depends on SB800_SATA_RAID
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help
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The RAID ROM requires that the MISC ROM is located between the range
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0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
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The CONFIG_ROM_SIZE must larger than 0x100000.
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endif
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endif #SOUTHBRIDGE_AMD_CIMX_SB800
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