555c3b1d9b
Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <boot/coreboot_tables.h>
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#include <console/uart.h>
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#include <drivers/uart/uart8250reg.h>
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#include <stdint.h>
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struct tegra210_uart {
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union {
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uint32_t thr; // Transmit holding register.
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uint32_t rbr; // Receive buffer register.
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uint32_t dll; // Divisor latch lsb.
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};
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union {
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uint32_t ier; // Interrupt enable register.
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uint32_t dlm; // Divisor latch msb.
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};
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union {
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uint32_t iir; // Interrupt identification register.
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uint32_t fcr; // FIFO control register.
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};
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uint32_t lcr; // Line control register.
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uint32_t mcr; // Modem control register.
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uint32_t lsr; // Line status register.
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uint32_t msr; // Modem status register.
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} __packed;
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static struct tegra210_uart * const uart_ptr =
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(void *)CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;
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static void tegra210_uart_tx_flush(void);
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static int tegra210_uart_tst_byte(void);
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static void tegra210_uart_init(void)
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{
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// Use a hardcoded divisor for now.
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const unsigned int divisor = 221;
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const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
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tegra210_uart_tx_flush();
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// Disable interrupts.
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write8(&uart_ptr->ier, 0);
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// Force DTR and RTS to high.
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write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
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// Set line configuration, access divisor latches.
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write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
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// Set the divisor.
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write8(&uart_ptr->dll, divisor & 0xff);
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write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
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// Hide the divisor latches.
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write8(&uart_ptr->lcr, line_config);
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// Enable FIFOs, and clear receive and transmit.
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write8(&uart_ptr->fcr,
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UART8250_FCR_FIFO_EN |
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UART8250_FCR_CLEAR_RCVR |
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UART8250_FCR_CLEAR_XMIT);
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}
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static void tegra210_uart_tx_byte(unsigned char data)
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{
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while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
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write8(&uart_ptr->thr, data);
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}
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static void tegra210_uart_tx_flush(void)
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{
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while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));
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}
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static unsigned char tegra210_uart_rx_byte(void)
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{
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if (!tegra210_uart_tst_byte())
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return 0;
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return read8(&uart_ptr->rbr);
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}
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static int tegra210_uart_tst_byte(void)
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{
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return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
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}
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void uart_init(unsigned int idx)
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{
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tegra210_uart_init();
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}
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void uart_tx_byte(unsigned int idx, unsigned char data)
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{
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tegra210_uart_tx_byte(data);
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}
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void uart_tx_flush(unsigned int idx)
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{
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tegra210_uart_tx_flush();
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}
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unsigned char uart_rx_byte(unsigned int idx)
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{
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return tegra210_uart_rx_byte();
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}
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void uart_fill_lb(void *data)
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{
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struct lb_serial serial;
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serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
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serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;
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serial.baud = get_uart_baudrate();
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serial.regwidth = 4;
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serial.input_hertz = uart_platform_refclk();
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serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
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lb_add_serial(&serial, data);
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lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
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}
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