55db955bcd
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
43 lines
735 B
Plaintext
43 lines
735 B
Plaintext
if BOARD_AOPEN_DXPLPLUSU
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_MPGA604
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select NORTHBRIDGE_INTEL_E7505
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select SOUTHBRIDGE_INTEL_I82870
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select SOUTHBRIDGE_INTEL_I82801DX
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select SUPERIO_SMSC_LPC47M10X
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# select HAVE_PIRQ_TABLE
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# select PIRQ_ROUTE
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select UDELAY_TSC
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_512
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select HW_SCRUBBER
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config MAINBOARD_DIR
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string
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default aopen/dxplplusu
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config MAINBOARD_PART_NUMBER
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string
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default "DXPL Plus-U"
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config IRQ_SLOT_COUNT
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int
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default 12
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config MAX_CPUS
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int
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default 4
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x0
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x0
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endif # BOARD_AOPEN_DXPLPLUSU
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