563fc0889f
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
316 lines
8.1 KiB
C
316 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* JEDEC Standard No. 21-C
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* Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules 2014
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* http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf
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*/
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#ifndef DEVICE_DRAM_DDR3L_H
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#define DEVICE_DRAM_DDR3L_H
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/**
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* @file ddr3.h
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*
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* \brief Utilities for decoding DDR3 SPDs
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*/
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#include <spd.h>
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#include <device/dram/common.h>
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#include <types.h>
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/**
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* Convenience definitions for SPD offsets
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*
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* @{
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*/
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#define SPD_DIMM_MOD_ID1 117
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#define SPD_DIMM_MOD_ID2 118
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#define SPD_DIMM_SERIAL_NUM 122
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#define SPD_DIMM_SERIAL_LEN 4
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#define SPD_DIMM_PART_NUM 128
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#define SPD_DIMM_PART_LEN 18
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/** @} */
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/**
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* \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP)
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*
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* Use this macro instead of printk(); for verbose RAM initialization messages.
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* When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically
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* disabled.
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* @{
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*/
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#if CONFIG(DEBUG_RAM_SETUP)
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#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
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#else
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#define printram(x, ...)
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#endif
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/** @} */
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/*
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* Module type (byte 3, bits 3:0) of SPD
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* This definition is specific to DDR3. DDR2 SPDs have a different structure.
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*/
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enum spd_dimm_type {
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SPD_DIMM_TYPE_UNDEFINED = 0x00,
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SPD_DIMM_TYPE_RDIMM = 0x01,
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SPD_DIMM_TYPE_UDIMM = 0x02,
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SPD_DIMM_TYPE_SO_DIMM = 0x03,
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SPD_DIMM_TYPE_MICRO_DIMM = 0x04,
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SPD_DIMM_TYPE_MINI_RDIMM = 0x05,
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SPD_DIMM_TYPE_MINI_UDIMM = 0x06,
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SPD_DIMM_TYPE_MINI_CDIMM = 0x07,
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SPD_DIMM_TYPE_72B_SO_UDIMM = 0x08,
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SPD_DIMM_TYPE_72B_SO_RDIMM = 0x09,
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SPD_DIMM_TYPE_72B_SO_CDIMM = 0x0a,
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SPD_DIMM_TYPE_LRDIMM = 0x0b,
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SPD_DIMM_TYPE_16B_SO_DIMM = 0x0c,
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SPD_DIMM_TYPE_32B_SO_DIMM = 0x0d,
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/* Masks to bits 3:0 to give the dimm type */
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SPD_DIMM_TYPE_MASK = 0x0f,
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};
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/**
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* \brief DIMM flags
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*
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* Characteristic flags for the DIMM, as presented by the SPD
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*/
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typedef union dimm_flags_st {
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/* The whole point of the union/struct construct is to allow us to clear
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* all the bits with one line: flags.raw = 0.
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* We do not care how these bits are ordered */
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struct {
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/* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See:
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* Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */
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unsigned int pins_mirrored:1;
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/* Module can work at 1.50V - All DIMMS must be 1.5V operable */
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unsigned int operable_1_50V:1;
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/* Module can work at 1.35V */
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unsigned int operable_1_35V:1;
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/* Module can work at 1.20V */
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unsigned int operable_1_25V:1;
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/* Has an 8-bit bus extension, meaning the DIMM supports ECC */
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unsigned int is_ecc:1;
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/* DLL-Off Mode Support */
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unsigned int dll_off_mode:1;
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/* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */
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unsigned int rzq6_supported:1;
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/* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */
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unsigned int rzq7_supported:1;
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/* Partial Array Self Refresh */
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unsigned int pasr:1;
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/* On-die Thermal Sensor Readout */
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unsigned int odts:1;
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/* Auto Self Refresh */
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unsigned int asr:1;
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/* Extended temperature range supported */
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unsigned int ext_temp_range:1;
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/* Operating at extended temperature requires 2X refresh rate */
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unsigned int ext_temp_refresh:1;
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/* Thermal sensor incorporated */
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unsigned int therm_sensor:1;
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};
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unsigned int raw;
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} dimm_flags_t;
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/**
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* \brief DIMM characteristics
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*
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* The characteristics of each DIMM, as presented by the SPD
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*/
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typedef struct dimm_attr_st {
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enum spd_memory_type dram_type;
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enum spd_dimm_type dimm_type;
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u16 cas_supported;
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/* Flags extracted from SPD */
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dimm_flags_t flags;
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/* SDRAM width */
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u8 width;
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/* Number of ranks */
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u8 ranks;
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/* Number or row address bits */
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u8 row_bits;
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/* Number or column address bits */
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u8 col_bits;
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/* Size of module in MiB */
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u32 size_mb;
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/* Latencies are in units of 1/256 ns */
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u32 tCK;
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u32 tAA;
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u32 tWR;
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u32 tRCD;
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u32 tRRD;
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u32 tRP;
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u32 tRAS;
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u32 tRC;
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u32 tRFC;
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u32 tWTR;
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u32 tRTP;
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u32 tFAW;
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u32 tCWL;
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u16 tCMD;
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u8 reference_card;
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/* XMP: Module voltage in mV */
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u16 voltage;
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/* XMP: max DIMMs per channel supported (1-4) */
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u8 dimms_per_channel;
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/* Manufacturer ID */
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u16 manufacturer_id;
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/* ASCII part number - NULL terminated */
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u8 part_number[17];
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/* Serial number */
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u8 serial[SPD_DIMM_SERIAL_LEN];
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} dimm_attr;
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enum ddr3_xmp_profile {
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DDR3_XMP_PROFILE_1 = 0,
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DDR3_XMP_PROFILE_2 = 1,
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};
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typedef u8 spd_raw_data[256];
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u16 spd_ddr3_calc_crc(u8 *spd, int len);
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u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
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int spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd_data);
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int spd_dimm_is_registered_ddr3(enum spd_dimm_type type);
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void dram_print_spd_ddr3(const dimm_attr *dimm);
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int spd_xmp_decode_ddr3(dimm_attr *dimm,
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spd_raw_data spd,
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enum ddr3_xmp_profile profile);
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enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
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const u16 selected_freq,
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const dimm_attr *info);
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/**
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* \brief Read double word from specified address
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*
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* Should be useful when doing an MRS to the DIMM
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*/
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static inline u32 volatile_read(volatile uintptr_t addr)
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{
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volatile u32 result;
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result = *(volatile u32 *)addr;
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return result;
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}
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/**
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* \brief Representation of an MRS command
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*
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* This represents an MRS command as seen by the DIMM. This is not a memory
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* address that can be read to generate an MRS command. The mapping of CPU
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* to memory pins is hardware-dependent.
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* \n
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* The idea is to generalize the MRS code, and only need a hardware-specific
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* function to map the MRS bits to CPU address bits. An MRS command can be
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* sent like:
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* @code{.c}
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* u32 addr;
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* mrs_cmd_t mrs;
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* chipset_enable_mrs_command_mode();
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* mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl)
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* if (rank_has_mirrorred_pins)
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* mrs = ddr3_mrs_mirror_pins(mrs);
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* addr = chipset_specific_get_mrs_addr(mrs);
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* volatile_read(addr);
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* @endcode
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*
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* The MRS representation has the following structure:
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* - cmd[15:0] = Address pins MA[15:0]
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* - cmd[18:16] = Bank address BA[2:0]
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*/
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typedef u32 mrs_cmd_t;
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enum ddr3_mr0_precharge {
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DDR3_MR0_PRECHARGE_SLOW = 0,
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DDR3_MR0_PRECHARGE_FAST = 1,
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};
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enum ddr3_mr0_mode {
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DDR3_MR0_MODE_NORMAL = 0,
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DDR3_MR0_MODE_TEST = 1,
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};
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enum ddr3_mr0_dll_reset {
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DDR3_MR0_DLL_RESET_NO = 0,
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DDR3_MR0_DLL_RESET_YES = 1,
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};
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enum ddr3_mr0_burst_type {
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DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0,
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DDR3_MR0_BURST_TYPE_INTERLEAVED = 1,
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};
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enum ddr3_mr0_burst_length {
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DDR3_MR0_BURST_LENGTH_8 = 0,
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DDR3_MR0_BURST_LENGTH_CHOP = 1,
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DDR3_MR0_BURST_LENGTH_4 = 2,
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};
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mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd,
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u8 write_recovery,
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enum ddr3_mr0_dll_reset dll_reset,
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enum ddr3_mr0_mode mode,
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u8 cas,
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enum ddr3_mr0_burst_type interleaved_burst,
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enum ddr3_mr0_burst_length burst_length);
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enum ddr3_mr1_qoff {
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DDR3_MR1_QOFF_ENABLE = 0,
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DDR3_MR1_QOFF_DISABLE = 1,
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};
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enum ddr3_mr1_tqds {
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DDR3_MR1_TQDS_DISABLE = 0,
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DDR3_MR1_TQDS_ENABLE = 1,
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};
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enum ddr3_mr1_write_leveling {
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DDR3_MR1_WRLVL_DISABLE = 0,
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DDR3_MR1_WRLVL_ENABLE = 1,
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};
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enum ddr3_mr1_rtt_nom {
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DDR3_MR1_RTT_NOM_OFF = 0,
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DDR3_MR1_RTT_NOM_RZQ4 = 1,
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DDR3_MR1_RTT_NOM_RZQ2 = 2,
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DDR3_MR1_RTT_NOM_RZQ6 = 3,
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DDR3_MR1_RTT_NOM_RZQ12 = 4,
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DDR3_MR1_RTT_NOM_RZQ8 = 5,
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};
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enum ddr3_mr1_additive_latency {
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DDR3_MR1_AL_DISABLE = 0,
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DDR3_MR1_AL_CL_MINUS_1 = 1,
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DDR3_MR1_AL_CL_MINUS_2 = 2,
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};
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enum ddr3_mr1_ods {
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DDR3_MR1_ODS_RZQ6 = 0,
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DDR3_MR1_ODS_RZQ7 = 1,
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};
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enum ddr3_mr1_dll {
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DDR3_MR1_DLL_ENABLE = 0,
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DDR3_MR1_DLL_DISABLE = 1,
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};
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mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff,
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enum ddr3_mr1_tqds tqds,
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enum ddr3_mr1_rtt_nom rtt_nom,
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enum ddr3_mr1_write_leveling write_leveling,
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enum ddr3_mr1_ods output_drive_strenght,
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enum ddr3_mr1_additive_latency additive_latency,
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enum ddr3_mr1_dll dll_disable);
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enum ddr3_mr2_rttwr {
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DDR3_MR2_RTTWR_OFF = 0,
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DDR3_MR2_RTTWR_RZQ4 = 1,
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DDR3_MR2_RTTWR_RZQ2 = 2,
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};
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enum ddr3_mr2_srt_range {
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DDR3_MR2_SRT_NORMAL = 0,
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DDR3_MR2_SRT_EXTENDED = 1,
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};
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enum ddr3_mr2_asr {
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DDR3_MR2_ASR_MANUAL = 0,
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DDR3_MR2_ASR_AUTO = 1,
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};
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mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr,
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enum ddr3_mr2_srt_range extended_temp,
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enum ddr3_mr2_asr self_refresh, u8 cas_cwl);
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mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr);
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mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd);
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#endif /* DEVICE_DRAM_DDR3L_H */
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