576f1cd44b
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
223 lines
6.9 KiB
Plaintext
223 lines
6.9 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/skylake
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# FSP Configuration
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "SkipExtGfxScan" = "1"
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# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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register "PmConfigSlpS3MinAssert" = "0x02"
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# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
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register "PmConfigSlpS4MinAssert" = "0x04"
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# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
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register "PmConfigSlpSusMinAssert" = "0x03"
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# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
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register "PmConfigSlpAMinAssert" = "0x03"
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# VR Settings Configuration for 4 Domains
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#+----------------+-----------+-----------+-------------+----------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-----------+-----------+-------------+----------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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# Enable x1 slot
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register "PcieRpEnable[7]" = "1"
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register "PcieRpClkReqSupport[7]" = "1"
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register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
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# Enable x4 slot
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register "PcieRpEnable[8]" = "1"
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
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# Enable Root port 6 and 13.
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register "PcieRpEnable[5]" = "1"
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register "PcieRpEnable[12]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[5]" = "1"
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register "PcieRpClkReqSupport[12]" = "1"
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# RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[5]" = "0"
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register "PcieRpClkReqNumber[12]" = "1"
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register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSpi0] = PchSerialIoPci,
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[PchSerialIoIndexSpi1] = PchSerialIoPci,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart1] = PchSerialIoPci,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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# PL2 override 25W
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register "power_limits_config" = "{
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.tdp_pl2_override = 25,
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Use default SD card detect GPIO configuration
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#register "sdcard_cd_gpio" = "GPP_A7"
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device domain 0 on
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device ref igpu on end
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device ref south_xhci on
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register "SsicPortEnable" = "1"
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register "usb2_ports" = "{
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[0] = USB2_PORT_MID(OC_SKIP), /* OTG */
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[1] = USB2_PORT_MID(OC3), /* Touch Pad */
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[2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */
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[3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */
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[4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */
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[5] = USB2_PORT_MID(OC0), /* Front Panel */
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[6] = USB2_PORT_MID(OC0), /* Front Panel */
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[7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
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[8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */
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[9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
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[10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */
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[11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */
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[12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
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[13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */
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}"
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register "usb3_ports" = "{
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[0] = USB3_PORT_DEFAULT(OC5), /* OTG */
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[1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */
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[2] = USB3_PORT_DEFAULT(OC3), /* Flex */
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[3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */
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[4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
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[5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
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[6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */
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[7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
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[8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */
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[9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */
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}"
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end
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device ref thermal on end
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device ref i2c0 on end
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device ref i2c1 on end
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device ref i2c2 on end
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device ref i2c3 on end
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device ref heci1 on end
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device ref sata on
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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[4] = 1,
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[5] = 1,
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[6] = 1,
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[7] = 1,
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}"
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end
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device ref uart2 on end
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device ref i2c5 on end
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device ref i2c4 on end
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device ref pcie_rp1 on end
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device ref uart0 on end
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device ref uart1 on end
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device ref gspi0 on end
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device ref gspi1 on end
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device ref hda on end
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device ref smbus on end
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device ref lpc_espi on
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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end
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device ref fast_spi on end
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device ref gbe on end
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end
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end
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