50bb68f2b6
This file is only static defines. Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
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#define _PLATFORM_GNB_PCIE_COMPLEX_H
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/**
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* @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
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*
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* GNB_GPP_PORT?_PORT_PRESENT
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* 0:Disable 1:Enable
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*
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* GNB_GPP_PORT?_SPEED_MODE
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* 0:Auto 1:GEN1 2:GEN2
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*
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* GNB_GPP_PORT?_LINK_ASPM
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* 0:Disable 1:L0s 2:L1 3:L0s+L1
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*
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* GNB_GPP_PORT?_CHANNEL_TYPE -
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* 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
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* 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
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*
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* GNB_GPP_PORT?_HOTPLUG_SUPPORT
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* 0:Disable 1:Basic 3:Enhanced
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*/
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/* GNB GPP 4 */
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#define GNB_GPP_PORT4_PORT_PRESENT 1
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#define GNB_GPP_PORT4_SPEED_MODE 2
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#define GNB_GPP_PORT4_LINK_ASPM 3
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#define GNB_GPP_PORT4_CHANNEL_TYPE 4
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#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
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/* GNB GPP 5 */
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#define GNB_GPP_PORT5_PORT_PRESENT 1
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#define GNB_GPP_PORT5_SPEED_MODE 2
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#define GNB_GPP_PORT5_LINK_ASPM 3
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#define GNB_GPP_PORT5_CHANNEL_TYPE 4
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#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
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/* GNB GPP 6 */
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#define GNB_GPP_PORT6_PORT_PRESENT 1
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#define GNB_GPP_PORT6_SPEED_MODE 2
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#define GNB_GPP_PORT6_LINK_ASPM 3
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#define GNB_GPP_PORT6_CHANNEL_TYPE 4
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#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
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/* GNB GPP 7 */
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#define GNB_GPP_PORT7_PORT_PRESENT 0
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#define GNB_GPP_PORT7_SPEED_MODE 2
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#define GNB_GPP_PORT7_LINK_ASPM 3
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#define GNB_GPP_PORT7_CHANNEL_TYPE 4
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#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
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/* GNB GPP 8 */
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#define GNB_GPP_PORT8_PORT_PRESENT 1
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#define GNB_GPP_PORT8_SPEED_MODE 2
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#define GNB_GPP_PORT8_LINK_ASPM 3
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#define GNB_GPP_PORT8_CHANNEL_TYPE 4
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#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
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#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
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