23d4d9f368
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
220 lines
5.8 KiB
C
220 lines
5.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SR5650_CMN_H__
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#define __SR5650_CMN_H__
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#include <device/pci_ops.h>
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#define NBMISC_INDEX 0x60
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#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
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#define NBMC_INDEX 0xE8
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#define NBPCIE_INDEX 0xE0
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#define L2CFG_INDEX 0xF0
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#define L1CFG_INDEX 0xF8
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#define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
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#define axindxc_reg(reg, mask, val) \
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alink_ax_indx(0, (reg), (mask), (val))
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#define AB_INDX 0xCD8
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#define AB_DATA (AB_INDX+4)
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#if ENV_PCI_SIMPLE_DEVICE
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static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
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#else
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static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
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#endif
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{
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pci_write_config32(dev, index_reg, index);
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return pci_read_config32(dev, index_reg + 0x4);
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
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u32 data)
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#else
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static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,
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u32 data)
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#endif
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{
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pci_write_config32(dev, index_reg, index);
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pci_write_config32(dev, index_reg + 0x4, data);
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
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#else
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static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
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#endif
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{
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return nb_read_index((nb_dev), NBMISC_INDEX, (index));
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
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#else
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static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
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u32 data)
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#endif
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{
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nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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nbmisc_write_index(nb_dev, reg_pos, reg);
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}
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
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#else
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static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
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#endif
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{
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return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
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#else
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static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
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#endif
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{
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nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
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#else
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static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
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#endif
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{
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return nb_read_index((nb_dev), NBMC_INDEX, (index));
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
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#else
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static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
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#endif
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{
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nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = htiu_read_index(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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htiu_write_index(nb_dev, reg_pos, reg);
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}
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = pci_read_config32(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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pci_write_config32(nb_dev, reg_pos, reg);
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}
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
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u8 mask, u8 val)
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#else
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static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,
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u8 mask, u8 val)
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#endif
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{
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u8 reg_old, reg;
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reg = reg_old = pci_read_config8(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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pci_write_config8(nb_dev, reg_pos, reg);
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}
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#else
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static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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nbmc_write_index(nb_dev, reg_pos, reg);
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}
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}
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#if ENV_PCI_SIMPLE_DEVICE
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static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
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u32 val)
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#else
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static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,
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u32 mask, u32 val)
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#endif
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{
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u32 reg_old, reg;
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reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
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reg &= ~mask;
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reg |= val;
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if (reg != reg_old) {
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nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
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}
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}
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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#endif /* __SR5650_CMN_H__ */
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