5817c56d19
Change-Id: I746ea7805bae553a146130994d8174aa2e189610 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef DEVICE_PNP_HWM5_CONF_H
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#define DEVICE_PNP_HWM5_CONF_H
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#include <device/pnp.h>
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#include <stdint.h>
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/* The address/data register pair for the indirect/indexed IO space of the
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* hardware monitor (HWM) that does temperature and voltage sensing and fan
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* control in ITE, Nuvoton and Winbond super IO chips aren't at offset 0 and 1
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* of the corresponding IO address region, but at offset 5 and 6. */
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/*
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* u8 pnp_read_hwm5_index(u16 port, u8 reg)
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* Description:
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* This routine reads indexed I/O registers. The reg byte is written
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* to the index register at I/O address = port + 5. The result is then
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* read from the data register at I/O address = port + 6.
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*
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* Parameters:
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* @param[in] u16 base = The I/O address of the port index register.
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* @param[in] u8 reg = The offset within the indexed space.
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* @param[out] u8 result = The value read back from the data register.
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*/
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static inline u8 pnp_read_hwm5_index(u16 base, u8 reg)
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{
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return pnp_read_index(base + 5, reg);
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}
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/*
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* void pnp_write_hwm5_index(u16 port, u8 reg, u8 value)
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* Description:
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* This routine writes indexed I/O registers. The reg byte is written
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* to the index register at I/O address = port + 5. The value byte is then
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* written to the data register at I/O address = port + 6.
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*
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* Parameters:
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* @param[in] u16 base = The address of the port index register.
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* @param[in] u8 reg = The offset within the indexed space.
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* @param[in] u8 value = The value to be written to the data register.
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*/
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static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value)
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{
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pnp_write_index(base + 5, reg, value);
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}
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#endif /* DEVICE_PNP_HWM5_CONF_H */
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