Set up the TPM decode to SPI prior to verstage. Enable LPC TPM and remove the mock data. Note, Kahlee TPM is on SPI, but decoded by the LPC block. BRANCH=none BUG=b:62103024 TEST=coreboot and Depthcharge reports TPM found. Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
64 lines
1.9 KiB
Plaintext
64 lines
1.9 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip soc/amd/stoneyridge
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
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}"
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device cpu_cluster 0 on
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device lapic 10 on end
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end
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device domain 0 on
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subsystemid 0x1022 0x1410 inherit
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 on end # PCIe Host Bridge
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device pci 2.1 on end # x4 PCIe slot
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device pci 2.2 on end # M.2 slot
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device pci 2.3 on end # M.2 slot
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device pci 2.4 on end # x1 PCIe slot
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device pci 2.5 on end # Cardreader
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# devices on the NB/SB Link, but on the same pci bus
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device pci 9.0 on end # PCIe Host Bridge
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device pci 9.2 on end # HDA
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device pci 10.0 on end # xHCI
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device pci 11.0 on end # SATA
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device pci 12.0 on end # EHCI
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device pci 14.0 on # SM
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chip drivers/generic/generic # dimm 0-0-0
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device i2c 50 on end
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end
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end # SM
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device pci 14.3 on
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end # LPC 0x790e
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device pci 14.7 on end # SD
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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end #domain
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end #chip soc/amd/stoneyridge
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