5840626cec
This patch is to perform software triggered RAM re-repair in the cold boot path. "RAM" actually refers to the CPU cache here (yeah, I know, but that's how the manuals call it). This is some magic hardware thing that must be done every time after applying power to the main CPU cores or their cache may have random failures in some very rare cases. BUG=chrome-os-partner:30430 BRANCH=nyan TEST=run cold reboot test on nyan. Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: I87869431e80e7bc66948a7f67f35e5b907993765 Original-Reviewed-on: https://chromium-review.googlesource.com/207362 Original-Tested-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> (cherry picked from commit d999f5ecc31d90c8dce1dd91533bc34ffd3c03f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iaee1d7f9fa8856f26d7ead70eaeeff9d80dbb181 Reviewed-on: http://review.coreboot.org/8415 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include "pmc.h"
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#include "power.h"
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#include "flow.h"
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static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
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static struct flow_ctlr * const flow = (void *)TEGRA_FLOW_BASE;
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static int partition_powered(int id)
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{
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return read32(&pmc->pwrgate_status) & (0x1 << id);
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}
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static int partition_clamp_on(int id)
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{
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return read32(&pmc->clamp_status) & (0x1 << id);
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}
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static void power_ungate_partition(uint32_t id)
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{
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printk(BIOS_INFO, "Ungating power partition %d.\n", id);
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if (!partition_powered(id)) {
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uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle);
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pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
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pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
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pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
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write32(pwrgate_toggle, &pmc->pwrgate_toggle);
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// Wait for the request to be accepted.
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while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
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;
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printk(BIOS_DEBUG, "Power gate toggle request accepted.\n");
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// Wait for the partition to be powered.
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while (!partition_powered(id))
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;
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// Wait for clamp off.
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while (partition_clamp_on(id))
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;
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}
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printk(BIOS_INFO, "Ungated power partition %d.\n", id);
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}
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void power_enable_and_ungate_cpu(void)
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{
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/*
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* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz),
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* set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s).
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*/
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write32((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
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uint32_t cntrl = read32(&pmc->cntrl);
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cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
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cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
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write32(cntrl, &pmc->cntrl);
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power_ungate_partition(POWER_PARTID_CRAIL);
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// Ungate power to the non-core parts of the fast cluster.
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power_ungate_partition(POWER_PARTID_C0NC);
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// Ungate power to CPU0 in the fast cluster.
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power_ungate_partition(POWER_PARTID_CE0);
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}
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int power_reset_status(void)
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{
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return read32(&pmc->rst_status) & 0x7;
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}
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void ram_repair(void)
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{
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// Request RAM repair for cluster 0
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setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
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// Poll for completion
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while (!(read32(&flow->ram_repair) & RAM_REPAIR_STS))
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;
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// Request RAM repair for cluster 1
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setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
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// Poll for completion
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while (!(read32(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
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;
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}
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