58901b6b66
Take codec out of reset (GPIO_PH1 aka CODEC_RST_L) and enable LDO2 (GPIO_PR2/KB_ROW2 aka AUDIO_ENABLE). Muxes are setup and the two GPIOs are set to output and driven high. BUG=chrome-os-partner:32582 BRANCH=none TEST=RealTek ALC5677 codec shows up in I2C6 scan at address 0x2D, can read/write registers. Change-Id: I236850452d401fd89b4f59eb03f132c0be32fb20 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fe3b0c1a3f5d6264b83d7a7e2363dc3f3235cbf Original-Change-Id: Iedce7bb9f8e61d3b8cd693fc5e567323d89f8046 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
86 lines
2.9 KiB
C
86 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/mmu.h>
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#include <boot/coreboot_tables.h>
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#include <device/device.h>
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#include <memrange.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/clock.h>
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#include <soc/funitcfg.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/padconfig.h>
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static const struct pad_config mmcpads[] = {
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/* MMC4 (eMMC) */
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PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE|PINMUX_PULL_DOWN, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT0, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT1, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT2, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT3, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT4, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT5, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT6, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
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};
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static const struct pad_config audio_codec_pads[] = {
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/* H1 is CODEC_RST_L and R2(ROW2) is AUDIO_ENABLE */
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PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN),
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PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN),
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};
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static const struct funit_cfg funits[] = {
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/* MMC on SDMMC4 controller at 48MHz. */
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FUNIT_CFG(SDMMC4, PLLP, 48000, mmcpads, ARRAY_SIZE(mmcpads)),
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/* I2C6 for audio, temp sensor, etc. Enable codec via GPIOs/muxes */
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FUNIT_CFG(I2C6, PLLP, 400, audio_codec_pads, ARRAY_SIZE(audio_codec_pads)),
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FUNIT_CFG_USB(USBD),
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};
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static void mainboard_init(device_t dev)
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{
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/* PLLD should be 2 * pixel clock (301620khz). */
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const uint32_t req_disp_clk = 301620 * 1000 * 2;
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uint32_t disp_clk;
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soc_configure_funits(funits, ARRAY_SIZE(funits));
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disp_clk = clock_display(req_disp_clk);
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if (disp_clk != req_disp_clk)
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printk(BIOS_DEBUG, "display clock: %u vs %u (r)\n", disp_clk,
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req_disp_clk);
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/* I2C6 bus (audio, etc.) */
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soc_configure_i2c6pad();
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i2c_init(I2C6_BUS);
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = "rush_ryu",
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.enable_dev = mainboard_enable,
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};
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