86da00db89
Include soc common lpss header file to resolve build error due to missing soc_lpss_controllers_list declaration. Also remove console header since it is unused. Change-Id: I2b2c82fc7592120993bc483d3061803cf75c7335 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37556 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <fsp/api.h>
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#include <intelblocks/lpss.h>
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#include <soc/ramstage.h>
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static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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PCH_DEVFN_I2C2,
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PCH_DEVFN_I2C3,
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PCH_DEVFN_I2C4,
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PCH_DEVFN_I2C5,
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PCH_DEVFN_GSPI0,
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PCH_DEVFN_GSPI1,
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PCH_DEVFN_GSPI2,
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PCH_DEVFN_UART0,
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PCH_DEVFN_UART1,
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PCH_DEVFN_UART2
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};
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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/* TODO: Update with UPD override as FSP matures */
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}
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/* Return list of SOC LPSS controllers */
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const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
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{
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*size = ARRAY_SIZE(serial_io_dev);
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return serial_io_dev;
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}
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