59143bbebd
Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
55 lines
1.4 KiB
Makefile
55 lines
1.4 KiB
Makefile
ifeq ($(CONFIG_CPU_SAMSUNG_EXYNOS5420),y)
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bootblock-y += spi.c alternate_cbfs.c
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bootblock-y += bootblock.c
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bootblock-y += pinmux.c timer.c power.c
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# Clock is required for UART
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bootblock-y += clock_init.c
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bootblock-y += clock.c
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bootblock-y += uart.c
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bootblock-y += wakeup.c
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bootblock-y += gpio.c
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romstage-y += spi.c alternate_cbfs.c
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romstage-y += smp.c
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romstage-y += clock.c
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romstage-y += clock_init.c
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romstage-y += pinmux.c # required by s3c24x0_i2c and uart.
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romstage-y += dmc_common.c
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romstage-y += dmc_init_ddr3.c
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romstage-y += power.c
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romstage-y += timer.c
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romstage-y += uart.c
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romstage-y += wakeup.c
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romstage-y += gpio.c
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romstage-y += i2c.c
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#romstage-y += wdt.c
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romstage-y += cbmem.c
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romstage-y += trustzone.c
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ramstage-y += spi.c alternate_cbfs.c
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ramstage-y += clock.c
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ramstage-y += clock_init.c
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ramstage-y += pinmux.c
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ramstage-y += power.c
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ramstage-y += uart.c
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ramstage-y += cpu.c
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ramstage-y += tmu.c
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ramstage-y += timer.c
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ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += dp.c dp_lowlevel.c fimd.c
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ramstage-y += usb.c
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rmodules_$(ARCH-ROMSTAGE-y)-y += timer.c
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CPPFLAGS_common += -Isrc/soc/samsung/common/include/
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CPPFLAGS_common += -Isrc/soc/samsung/exynos5420/include/
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
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util/exynos/variable_cksum.py $< $<.cksum
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cat 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
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endif
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