Files
system76-coreboot/src
Wonkyu Kim 5943117647 soc/intel/tigerlake: Configure RP setting
Add LTR and AER configuration to the root ports config.

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:52:16 +00:00
..
2020-04-13 23:32:27 +00:00
2020-04-13 23:39:29 +00:00
2020-04-10 00:10:58 +00:00
2020-04-13 23:32:15 +00:00