59a621abc7
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
63 lines
1.3 KiB
Makefile
63 lines
1.3 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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# all (bootblock, verstage, romstage, postcar, ramstage)
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all-y += gspi.c
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all-y += i2c.c
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all-y += pmutil.c
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all-y += spi.c
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all-y += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += gpio.c
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bootblock-y += p2sb.c
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romstage-y += espi.c
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romstage-y += meminit.c
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romstage-y += gpio.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += dptf.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += lockdown.c
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ramstage-y += me.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-y += soundwire.c
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ramstage-y += systemagent.c
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ramstage-y += xhci.c
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ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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smm-y += elog.c
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smm-y += xhci.c
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verstage-y += gpio.c
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
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endif
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