5a2feeda39
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CEZANNE_CHIP_H
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#define CEZANNE_CHIP_H
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#include <amdblocks/chip.h>
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#include <soc/i2c.h>
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#include <soc/southbridge.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <types.h>
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#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
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struct soc_amd_cezanne_config {
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struct soc_amd_common_config common_config;
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u8 i2c_scl_reset;
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struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
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u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT];
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/* Enable S0iX support */
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bool s0ix_enable;
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enum {
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DOWNCORE_AUTO = 0,
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DOWNCORE_1 = 1, /* Run with 1 physical core */
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DOWNCORE_2 = 3, /* Run with 2 physical cores */
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DOWNCORE_3 = 4, /* Run with 3 physical cores */
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DOWNCORE_4 = 6, /* Run with 4 physical cores */
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DOWNCORE_5 = 8, /* Run with 5 physical cores */
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DOWNCORE_6 = 9, /* Run with 6 physical cores */
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DOWNCORE_7 = 10, /* Run with 7 physical cores */
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} downcore_mode;
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bool disable_smt; /* disable second thread on all physical cores */
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uint8_t stt_control;
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uint8_t stt_pcb_sensor_count;
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uint16_t stt_min_limit;
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uint16_t stt_m1;
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uint16_t stt_m2;
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uint16_t stt_m3;
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uint16_t stt_m4;
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uint16_t stt_m5;
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uint16_t stt_m6;
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uint16_t stt_c_apu;
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uint16_t stt_c_gpu;
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uint16_t stt_c_hs2;
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uint16_t stt_alpha_apu;
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uint16_t stt_alpha_gpu;
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uint16_t stt_alpha_hs2;
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uint16_t stt_skin_temp_apu;
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uint16_t stt_skin_temp_gpu;
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uint16_t stt_skin_temp_hs2;
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uint16_t stt_error_coeff;
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uint16_t stt_error_rate_coefficient;
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uint8_t stapm_boost;
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uint32_t stapm_time_constant_s;
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uint32_t apu_only_sppt_limit;
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uint32_t sustained_power_limit_mW;
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uint32_t fast_ppt_limit_mW;
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uint32_t slow_ppt_limit_mW;
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uint32_t slow_ppt_time_constant_s;
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uint32_t thermctl_limit_degreeC;
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uint8_t smartshift_enable;
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uint8_t system_configuration;
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uint8_t cppc_ctrl;
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uint8_t cppc_perf_limit_max_range;
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uint8_t cppc_perf_limit_min_range;
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uint8_t cppc_epp_max_range;
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uint8_t cppc_epp_min_range;
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uint8_t cppc_preferred_cores;
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/* telemetry settings */
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uint32_t telemetry_vddcrvddfull_scale_current_mA;
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uint32_t telemetry_vddcrvddoffset;
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uint32_t telemetry_vddcrsocfull_scale_current_mA;
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uint32_t telemetry_vddcrsocoffset;
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/* Enable dptc for tablet mode (0 = disable, 1 = enable) */
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uint8_t dptc_enable;
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/* STAPM Configuration for tablet mode (need enable dptc_enable first) */
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uint32_t fast_ppt_limit_tablet_mode_mW;
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uint32_t slow_ppt_limit_tablet_mode_mW;
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uint32_t sustained_power_limit_tablet_mode_mW;
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uint32_t thermctl_limit_tablet_mode_degreeC;
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/* The array index is the general purpose PCIe clock output number. Values in here
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aren't the values written to the register to have the default to be always on. */
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enum {
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GPP_CLK_ON, /* GPP clock always on; default */
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GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
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GPP_CLK_OFF, /* GPP clk off */
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} gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
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/* performance policy for the PCIe links: power consumption vs. link speed */
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enum {
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DXIO_PSPP_DISABLED = 0,
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DXIO_PSPP_PERFORMANCE,
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DXIO_PSPP_BALANCED,
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DXIO_PSPP_POWERSAVE,
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} pspp_policy;
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uint8_t usb_phy_custom;
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struct usb_phy_config usb_phy;
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};
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#endif /* CEZANNE_CHIP_H */
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