5cdaa3305e
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
78 lines
2.0 KiB
Makefile
78 lines
2.0 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2017-present Facebook, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOC_CAVIUM_CN81XX),y)
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# bootblock
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bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock_custom.S
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bootblock-y += bootblock.c
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bootblock-y += twsi.c
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bootblock-y += clock.c
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bootblock-y += gpio.c
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bootblock-y += timer.c
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bootblock-y += spi.c
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bootblock-y += uart.c
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bootblock-y += cpu.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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endif
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################################################################################
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# romstage
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romstage-y += twsi.c
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romstage-y += clock.c
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romstage-y += gpio.c
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romstage-y += timer.c
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romstage-y += spi.c
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romstage-y += uart.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-< += cpu.c
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romstage-y += sdram.c
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romstage-y += mmu.c
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romstage-y += ../common/cbmem.c
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# BDK coreboot interface
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romstage-y += ../common/bdk-coreboot.c
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################################################################################
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# ramstage
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ramstage-y += twsi.c
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ramstage-y += clock.c
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ramstage-y += gpio.c
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ramstage-y += timer.c
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ramstage-y += spi.c
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ramstage-y += uart.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += sdram.c
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ramstage-y += soc.c
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ramstage-y += cpu.c
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ramstage-y += cpu_secondary.S
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ramstage-y += ecam0.c
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ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
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# BDK coreboot interface
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ramstage-y += ../common/bdk-coreboot.c
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BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0
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CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
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endif
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