Sven Schnelle 5d9a83c9f0 log ec data with DEBUG_SPEW ...

Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)

2011-06-12 17:13:51 +02:00

..

arch/x86

We don't have pausing versions of single-IO instructions.

2011-05-23 22:48:13 +00:00

boot

more ifdef -> if fixes.

2011-04-21 21:26:58 +00:00

console

Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an

2011-04-26 23:47:04 +00:00

cpu

Cosmetic cleanup.

2011-05-15 22:10:15 +00:00

devices

more ifdef -> if fixes

2011-04-21 20:45:45 +00:00

drivers

Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an

2011-04-26 23:47:04 +00:00

ec

log ec data with DEBUG_SPEW

2011-06-12 17:13:51 +02:00

include

SMM: add defines for APM_CNT register

2011-06-07 22:01:29 +02:00

lib

Change read_option() to a macro that wraps some API uglyness

2011-05-10 21:53:13 +00:00

mainboard

H8 EC: add volume CMOS setting

2011-06-09 10:05:46 +02:00

northbridge

This patch sets max freq defaults for ddr2 and ddr3for fam10.

2011-06-03 19:59:52 +00:00

pc80

Change read_option() to a macro that wraps some API uglyness

2011-05-10 21:53:13 +00:00

southbridge

Add ACPI automatic PIC/APIC interrupt routing logic for ck804

2011-06-10 19:44:04 +02:00

superio

some ifdef --> if fixes

2011-04-21 20:24:43 +00:00

vendorcode

trivial remove blanks at the end of line

2011-06-01 02:00:30 +00:00

Kconfig

Add option 'compress ramstage'

2011-05-02 19:53:04 +00:00

Kconfig.deprecated_options

some ifdef --> if fixes

2011-04-21 20:24:43 +00:00