Store LID status into LIDS and change device name to LID0. Then Intel driver can reference it. BUG=b:151134069 TEST=check LID status by evtest Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
188 lines
3.6 KiB
Plaintext
188 lines
3.6 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (EC0)
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{
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Name (_HID, EisaId ("PNP0C09"))
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Name (_UID, 1)
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Name (_GPE, EC_SCI_GPI)
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Name (_STA, 0xf)
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Name (DBUG, Zero)
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Name (_CRS, ResourceTemplate() {
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IO (Decode16,
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CONFIG_EC_BASE_ACPI_DATA,
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CONFIG_EC_BASE_ACPI_DATA,
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4, 4)
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IO (Decode16,
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CONFIG_EC_BASE_ACPI_COMMAND,
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CONFIG_EC_BASE_ACPI_COMMAND,
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4, 4)
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})
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/* Handle registration of EmbeddedControl region */
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Name (EREG, Zero)
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OperationRegion (ERAM, EmbeddedControl, 0, 0xff)
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Method (_REG, 2)
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{
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/* Indicate region is registered */
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EREG = Arg1
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/* Store initial value for power status */
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ECPR = R (PWSR)
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/* Indicate to EC that OS is ready for queries */
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W (ERDY, Arg1)
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/* Indicate that the OS supports S0ix */
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W (CSOS, One)
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/* Tell EC to stop emulating PS/2 mouse */
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W (PS2M, Zero)
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/* Enable DPTF support if enabled in devicetree */
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If (\DPTE == One) {
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W (DWST, Arg1)
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}
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/* Initialize UCSI */
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^UCSI.INIT ()
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// Initialize LID switch state
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Store (R (P1LC), \LIDS)
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}
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/*
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* Find bitmask for field
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* Arg0 = EC field structure
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* Arg1 = Value
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*/
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Method (EBIT, 2, NotSerialized)
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{
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Local0 = DeRefOf (Arg0[1]) /* Mask */
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Local1 = Arg1 & Local0
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FindSetRightBit (Local0, Local2)
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If (Local2) {
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Local1 >>= Local2 - 1
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}
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Return (Local1)
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}
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/*
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* READ or WRITE from EC region
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* Arg0 = EC field structure
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* Arg1 = Value to write
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*/
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Method (ECRW, 2, Serialized, 2)
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{
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If (!EREG) {
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Return (Zero)
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}
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Local0 = DeRefOf (Arg0[0]) /* Byte offset */
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Local1 = DeRefOf (Arg0[1]) /* Mask */
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Local2 = DeRefOf (Arg0[2]) /* Read/Write */
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OperationRegion (ERAM, EmbeddedControl, Local0, 2)
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Field (ERAM, ByteAcc, Lock, WriteAsZeros)
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{
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BYT1, 8,
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BYT2, 8,
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}
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If (Local2 == RD) {
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/* Read first byte */
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Local3 = BYT1
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/* Read second byte if needed */
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FindSetLeftBit (Local1, Local4)
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If (Local4 > 8) {
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Local4 = BYT2
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Local4 <<= 8
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Local3 |= Local4
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}
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Local5 = EBIT (Arg0, Local3)
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If (DBUG) {
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Printf ("ECRD %o = %o", Local0, Local5)
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}
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Return (Local5)
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} ElseIf (Local2 == WR) {
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/* Write byte */
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If (DBUG) {
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Printf ("ECWR %o = %o", Local0, Arg1)
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}
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BYT1 = Arg1
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}
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Return (Zero)
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}
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/*
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* Read a field from EC
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* Arg0 = EC field structure
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*/
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Method (R, 1, Serialized, 2)
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{
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Return (ECRW (Arg0, Zero))
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}
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/*
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* Write value to a field from EC
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* Arg0 = EC field structure
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* Arg1 = Value to write
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*/
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Method (W, 2, Serialized, 2)
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{
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Return (ECRW (Arg0, Arg1))
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}
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/*
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* Tell EC that the OS is entering or exiting S0ix
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*/
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Method (S0IX, 1, Serialized)
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{
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If (Arg0) {
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Printf ("EC Enter S0ix")
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W (CSEX, One)
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/*
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* Read back from EC RAM after enabling S0ix
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* to prevent EC from aborting S0ix entry.
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*/
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R (EVT1)
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} Else {
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Printf ("EC Exit S0ix")
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W (CSEX, Zero)
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}
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}
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#include "ec_dev.asl"
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#include "ec_ram.asl"
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#include "ac.asl"
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#include "battery.asl"
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#include "event.asl"
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#include "lid.asl"
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#include "platform.asl"
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#include "vbtn.asl"
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#include "ucsi.asl"
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#ifdef EC_ENABLE_DPTF
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#include "dptf.asl"
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#endif
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#ifdef EC_ENABLE_PRIVACY
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#include "privacy.asl"
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#endif
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}
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