5e597572ef
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
80 lines
2.3 KiB
C
80 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <string.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "southbridge/intel/i82801ix/nvs.h"
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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/* Enable both COM ports */
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gnvs->cmap = 0x01;
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gnvs->cmbp = 0x01;
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/* IGD Displays */
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gnvs->ndid = 0; /* Will use default of 0x00000400. */
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* LAPIC_NMI */
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
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current, 0,
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MP_IRQ_POLARITY_HIGH |
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MP_IRQ_TRIGGER_EDGE, 0x01);
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
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current, 1, MP_IRQ_POLARITY_HIGH |
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MP_IRQ_TRIGGER_EDGE, 0x01);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
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return current;
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}
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