ffa710b9dd
The port is based on the F2A85-M, the main differences are: - 2 DDR3 dimms - 2 PS/2 ports - 2*USB2.0 and 2*USB3.0 ports - 3+2 phase VRM - 6 channel audio - 6 SATA ports - ASP1206 VRM controller - Bolton D4 chipset - no optical SPDIF/IO Successfully booted configurations: -RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0 -CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland) -OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019 -SeaBIOS: 1.12 and 1.13 Known problems: - IRQ routing is done incorrect way - common problem of fam15h boards - Windows 7 can't boot because of the incomplete ACPI implementation Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <string.h>
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static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
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u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
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u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu)
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{
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pirq_info->bus = bus;
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pirq_info->devfn = devfn;
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pirq_info->irq[0].link = link0;
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pirq_info->irq[0].bitmap = bitmap0;
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pirq_info->irq[1].link = link1;
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pirq_info->irq[1].bitmap = bitmap1;
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pirq_info->irq[2].link = link2;
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pirq_info->irq[2].bitmap = bitmap2;
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pirq_info->irq[3].link = link3;
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pirq_info->irq[3].bitmap = bitmap3;
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pirq_info->slot = slot;
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pirq_info->rfu = rfu;
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}
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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struct irq_routing_table *pirq;
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struct irq_info *pirq_info;
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u32 slot_num;
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u8 sum = 0;
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int i;
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/* Align the table to be 16 byte aligned. */
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addr = ALIGN_UP(addr, 16);
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/* This table must be between 0xf0000 & 0x100000 */
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printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
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pirq = (void *)(addr);
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pirq->signature = PIRQ_SIGNATURE;
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pirq->version = PIRQ_VERSION;
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pirq->rtr_bus = 0;
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pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
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pirq->exclusive_irqs = 0;
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pirq->rtr_vendor = 0x1002;
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pirq->rtr_device = 0x4384;
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pirq->miniport_data = 0;
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memset(pirq->rfu, 0, sizeof(pirq->rfu));
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pirq_info = (void *)(&pirq->slots);
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slot_num = 0;
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/* pci bridge */
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write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
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0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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pirq_info++;
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slot_num++;
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pirq->size = 32 + 16 * slot_num;
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{
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const u8 *const v = (u8 *)(pirq);
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for (i = 0; i < pirq->size; i++)
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sum += v[i];
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}
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sum = pirq->checksum - sum;
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if (sum != pirq->checksum)
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pirq->checksum = sum;
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printk(BIOS_INFO, "%s done.\n", __func__);
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return (unsigned long)pirq_info;
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}
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