5eef7b34c1
This will be used by new Roda boards. Four UARTs and PS/2 keyboard and mouse are exposed to ACPI. Since our boards only use the environment controller part, most of the usual pnp interfaces are untested. Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
169 lines
4.7 KiB
Plaintext
169 lines
4.7 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013, 2016 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the IT8783E/F SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x0 FDC Not implemented
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* 0x1 UARTA Implemented, untested
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* 0x2 UARTB Implemented, untested
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* 0x3 PP Not implemented
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* 0x4 EC Not implemented
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* 0x5 KBC Implemented, untested
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* 0x6 MOUSE Implemented, untested
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* 0x7 GPIO Not implemented
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* 0x8 UARTC Implemented, untested
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* 0x9 UARTD Implemented, untested
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* 0xa UARTE Not implemented
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* 0xb UARTF Not implemented
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* 0xc CIR Not implemented
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* IT8783EF_SHOW_UARTA If defined, UARTA will be exposed.
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* IT8783EF_SHOW_UARTB If defined, UARTB will be exposed.
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* IT8783EF_SHOW_UARTC If defined, UARTC will be exposed.
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* IT8783EF_SHOW_UARTD If defined, UARTD will be exposed.
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* IT8783EF_SHOW_KBC If defined, the KBC will be exposed.
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* IT8783EF_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME IT8783EF
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#include <superio/acpi/pnp.asl>
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#define CONFIGURE_CONTROL CCTL
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("ITE IT8783E/F Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* Mutex for accesses to the configuration ports */
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Mutex(CRMX, 1)
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x02),
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CONFIGURE_CONTROL, 8, /* Global configure control */
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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}
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Method (_CRS)
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{
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/* Announce the used i/o ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x01
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#define PNP_ENTER_MAGIC_3RD 0x55
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#if SUPERIO_PNP_BASE == 0x2e
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#define PNP_ENTER_MAGIC_4TH 0x55
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#else
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#define PNP_ENTER_MAGIC_4TH 0xaa
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#endif
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#define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
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#define PNP_EXIT_SPECIAL_VAL 0x02
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#include <superio/acpi/pnp_config.asl>
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#ifdef IT8783EF_SHOW_UARTA
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 1
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8783EF_SHOW_UARTB
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8783EF_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN 5
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#ifdef IT8783EF_SHOW_PS2M
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#define SUPERIO_KBC_PS2LDN 6
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#endif
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef IT8783EF_SHOW_UARTC
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 8
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8783EF_SHOW_UARTD
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 9
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#include <superio/acpi/pnp_uart.asl>
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#endif
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}
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