a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
40 lines
1.8 KiB
C
40 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOUTHBRIDGE_AMD_CS5536
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#define _SOUTHBRIDGE_AMD_CS5536
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#define MAX_UNWANTED_VPCI 8 /* increase if needed */
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struct southbridge_amd_cs5536_config {
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unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
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unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
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unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */
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unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
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unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
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unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */
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unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
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unsigned char com1_enable; /* enable COM1 */
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unsigned int com1_address; /* e.g. 0x3F8 */
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unsigned int com1_irq; /* e.g. 4 */
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unsigned char com2_enable; /* enable COM2 */
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unsigned int com2_address; /* e.g. 0x2F8 */
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unsigned int com2_irq; /* e.g. 3 */
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unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */
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};
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#endif /* _SOUTHBRIDGE_AMD_CS5536 */
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