5f66b52464
The TrustZone carve-out needs to be taken into account when
determining the memory layout. However, things are complicated
by the fact that TZ carve-out registers are not accessible by
the AVP.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and booted to end of ramstage. Noted that denver cores
can read TZ registers while AVP doesn't bother.
Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207835
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494
Reviewed-on: http://review.coreboot.org/8593
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
134 lines
4.9 KiB
C
134 lines
4.9 KiB
C
/*
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* Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_MC_H__
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#define __SOC_NVIDIA_TEGRA132_MC_H__
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#include <stddef.h>
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#include <stdint.h>
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// Memory Controller registers we need/care about
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struct tegra_mc_regs {
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uint32_t rsvd_0x0[4]; /* 0x00 */
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uint32_t smmu_config; /* 0x10 */
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uint32_t smmu_tlb_config; /* 0x14 */
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uint32_t smmu_ptc_config; /* 0x18 */
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uint32_t smmu_ptb_asid; /* 0x1c */
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uint32_t smmu_ptb_data; /* 0x20 */
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uint32_t rsvd_0x24[3]; /* 0x24 */
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uint32_t smmu_tlb_flush; /* 0x30 */
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uint32_t smmu_ptc_flush; /* 0x34 */
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uint32_t rsvd_0x38[6]; /* 0x38 */
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uint32_t emem_cfg; /* 0x50 */
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uint32_t emem_adr_cfg; /* 0x54 */
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uint32_t emem_adr_cfg_dev0; /* 0x58 */
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uint32_t emem_adr_cfg_dev1; /* 0x5c */
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uint32_t rsvd_0x60[1]; /* 0x60 */
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uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */
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uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */
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uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */
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uint32_t security_cfg0; /* 0x70 */
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uint32_t security_cfg1; /* 0x74 */
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uint32_t rsvd_0x78[6]; /* 0x78 */
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uint32_t emem_arb_cfg; /* 0x90 */
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uint32_t emem_arb_outstanding_req; /* 0x94 */
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uint32_t emem_arb_timing_rcd; /* 0x98 */
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uint32_t emem_arb_timing_rp; /* 0x9c */
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uint32_t emem_arb_timing_rc; /* 0xa0 */
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uint32_t emem_arb_timing_ras; /* 0xa4 */
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uint32_t emem_arb_timing_faw; /* 0xa8 */
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uint32_t emem_arb_timing_rrd; /* 0xac */
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uint32_t emem_arb_timing_rap2pre; /* 0xb0 */
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uint32_t emem_arb_timing_wap2pre; /* 0xb4 */
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uint32_t emem_arb_timing_r2r; /* 0xb8 */
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uint32_t emem_arb_timing_w2w; /* 0xbc */
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uint32_t emem_arb_timing_r2w; /* 0xc0 */
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uint32_t emem_arb_timing_w2r; /* 0xc4 */
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uint32_t rsvd_0xc8[2]; /* 0xc8 */
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uint32_t emem_arb_da_turns; /* 0xd0 */
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uint32_t emem_arb_da_covers; /* 0xd4 */
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uint32_t emem_arb_misc0; /* 0xd8 */
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uint32_t emem_arb_misc1; /* 0xdc */
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uint32_t emem_arb_ring1_throttle; /* 0xe0 */
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uint32_t emem_arb_ring3_throttle; /* 0xe4 */
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uint32_t emem_arb_override; /* 0xe8 */
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uint32_t emem_arb_rsv; /* 0xec */
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uint32_t rsvd_0xf0[1]; /* 0xf0 */
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uint32_t clken_override; /* 0xf4 */
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uint32_t timing_control_dbg; /* 0xf8 */
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uint32_t timing_control; /* 0xfc */
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uint32_t stat_control; /* 0x100 */
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uint32_t rsvd_0x104[65]; /* 0x104 */
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uint32_t emem_arb_isochronous_0; /* 0x208 */
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uint32_t emem_arb_isochronous_1; /* 0x20c */
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uint32_t emem_arb_isochronous_2; /* 0x210 */
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uint32_t rsvd_0x214[38]; /* 0x214 */
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uint32_t dis_extra_snap_levels; /* 0x2ac */
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uint32_t rsvd_0x2b0[90]; /* 0x2b0 */
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uint32_t video_protect_vpr_override; /* 0x418 */
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uint32_t rsvd_0x41c[93]; /* 0x41c */
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uint32_t video_protect_vpr_override1; /* 0x590 */
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uint32_t rsvd_0x594[29]; /* 0x594 */
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uint32_t display_snap_ring; /* 0x608 */
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uint32_t rsvd_0x60c[15]; /* 0x60c */
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uint32_t video_protect_bom; /* 0x648 */
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uint32_t video_protect_size_mb; /* 0x64c */
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uint32_t video_protect_reg_ctrl; /* 0x650 */
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uint32_t rsvd_0x654[4]; /* 0x654 */
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uint32_t emem_cfg_access_ctrl; /* 0x664 */
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uint32_t rsvd_0x668[2]; /* 0x668 */
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uint32_t sec_carveout_bom; /* 0x670 */
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uint32_t sec_carveout_size_mb; /* 0x674 */
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uint32_t sec_carveout_reg_ctrl; /* 0x678 */
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uint32_t rsvd_0x67c[187]; /* 0x67c */
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uint32_t emem_arb_override_1; /* 0x968 */
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uint32_t rsvd_0x96c[3]; /* 0x96c */
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uint32_t video_protect_bom_adr_hi; /* 0x978 */
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uint32_t rsvd_0x97c[2]; /* 0x97c */
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uint32_t video_protect_gpu_override_0; /* 0x984 */
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uint32_t video_protect_gpu_override_1; /* 0x988 */
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uint32_t rsvd_0x98c[5]; /* 0x98c */
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uint32_t mts_carveout_bom; /* 0x9a0 */
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uint32_t mts_carveout_size_mb; /* 0x9a4 */
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uint32_t mts_carveout_adr_hi; /* 0x9a8 */
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uint32_t mts_carveout_reg_ctrl; /* 0x9ac */
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uint32_t rsvd_0x9b0[4]; /* 0x9b0 */
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uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */
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uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */
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uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */
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uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */
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uint32_t rsvd_0x9d0[1]; /* 0x9d0 */
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uint32_t sec_carveout_adr_hi; /* 0x9d4 */
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};
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enum {
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MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
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MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
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MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
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MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
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MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
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MC_TIMING_CONTROL_TIMING_UPDATE = 1,
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};
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check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4);
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#endif /* __SOC_NVIDIA_TEGRA132_MC_H__ */
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