5fc0afbc17
FADT duty_width/duty_offset fields, together with P_CNT (previously P_BLK) IO address are provided with _PTC entry. FADT p_lvl2/3_lat fields had values that disabled C2/C3 state transitions so _CST entries are not required. Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
35 lines
764 B
C
35 lines
764 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <device/device.h>
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#include "i82371eb.h"
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static void generate_cpu_entry(int cpu)
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{
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acpigen_write_processor_device(cpu);
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/* bit 1:3 in PCNTRL reg (pmbase+0x10) */
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acpigen_write_PTC(3, 1, DEFAULT_PMBASE + PCNTRL);
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acpigen_write_processor_device_end();
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}
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void generate_cpu_entries(const struct device *device)
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{
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int cpu;
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int numcpus = dev_count_cpu();
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printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);
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/* without the outer scope, further ssdt addition will end up
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* within the processor statement */
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acpigen_write_scope("\\_SB");
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for (cpu = 0; cpu < numcpus; cpu++)
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generate_cpu_entry(cpu);
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acpigen_pop_len();
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}
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