5fed693a52
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
132 lines
4.5 KiB
Makefile
132 lines
4.5 KiB
Makefile
################################################################################
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 The ChromiumOS Authors
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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################################################################################
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################################################################################
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## RISC-V specific options
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################################################################################
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ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
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check-ramstage-overlap-regions += stack
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endif
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riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
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riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
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COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
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COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
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################################################################################
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## bootblock
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################################################################################
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
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bootblock-y += id.S
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$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
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bootblock-y = bootblock.S stages.c
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bootblock-y += trap_util.S
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bootblock-y += trap_handler.c
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bootblock-y += mcall.c
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bootblock-y += virtual_memory.c
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bootblock-y += boot.c
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bootblock-y += misc.c
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bootblock-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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$(objcbfs)/bootblock.debug: $$(bootblock-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
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-T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \
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$(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock)
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bootblock-c-ccopts += $(riscv_flags)
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bootblock-S-ccopts += $(riscv_asm_flags)
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endif
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################################################################################
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## romstage
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################################################################################
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ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
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romstage-y += boot.c
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romstage-y += stages.c
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romstage-y += misc.c
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romstage-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
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# Build the romstage
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$(objcbfs)/romstage.debug: $$(romstage-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)
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romstage-c-ccopts += $(riscv_flags)
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romstage-S-ccopts += $(riscv_asm_flags)
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endif
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################################################################################
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## ramstage
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################################################################################
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ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
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ramstage-y =
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ramstage-y += virtual_memory.c
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ramstage-y += stages.c
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ramstage-y += misc.c
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ramstage-y += boot.c
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ramstage-y += tables.c
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ramstage-y += payload.S
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ramstage-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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$(eval $(call create_class_compiler,rmodules,riscv))
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ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
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# Build the ramstage
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$(objcbfs)/ramstage.debug: $$(ramstage-objs)
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)
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ramstage-c-ccopts += $(riscv_flags)
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ramstage-S-ccopts += $(riscv_asm_flags)
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endif
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