5ff7c13e85
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
350 lines
8.0 KiB
C
350 lines
8.0 KiB
C
#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include <cpu/amd/gx2def.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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#if 0
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void bug645(void)
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{
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msr_t msr;
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rdmsr(CPU_ID_CONFIG);
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msr.whatever |= ID_CONFIG_SERIAL_SET;
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wrmsr(msr);
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}
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void bug573(void)
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{
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msr_t msr;
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.eax &= 0xfff3;
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wrmsr(MC_GLD_MSR_PM);
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}
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#endif
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/* pcideadlock
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*
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* Bugtool #465 and #609
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* PCI cache deadlock
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* There is also fix code in cache and PCI functions. This bug is very is pervasive.
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*/
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static void pcideadlock(void)
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{
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msr_t msr;
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/* forces serialization of all load misses. Setting this bit prevents the
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* DM pipe from backing up if a read request has to be held up waiting
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* for PCI writes to complete.
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*/
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msr = rdmsr(CPU_DM_CONFIG0);
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msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
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wrmsr(CPU_DM_CONFIG0, msr);
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/* interlock instruction fetches to WS regions with data accesses.
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* This prevents an instruction fetch from going out to PCI if the
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* data side is about to make a request.
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*/
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msr = rdmsr(CPU_IM_CONFIG);
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msr.lo |= IM_CONFIG_LOWER_QWT_SET;
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wrmsr(CPU_IM_CONFIG, msr);
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/* write serialize memory hole to PCI. Need to unWS when something is
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* shadowed regardless of cachablility.
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*/
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msr.lo = 0x021212121;
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msr.hi = 0x021212121;
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wrmsr( CPU_RCONF_A0_BF, msr);
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wrmsr( CPU_RCONF_C0_DF, msr);
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wrmsr( CPU_RCONF_E0_FF, msr);
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}
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/* CPUbug784
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*
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* Bugtool #784 + #792
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*
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* Fix CPUID instructions for < 3.0 CPUs
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*/
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static void bug784(void)
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{
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msr_t msr;
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//static char *name = "Geode by NSC";
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/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
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* would do this -- the OS can figure this type of stuff out!
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*/
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msr = rdmsr(0x3006);
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msr.hi = 0x646f6547;
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wrmsr(0x3006, msr);
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msr = rdmsr(0x3007);
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msr.hi = 0x79622065;
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msr.lo = 0x43534e20;
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wrmsr(0x3007, msr);
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msr = rdmsr(0x3002);
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wrmsr(0x3008, msr);
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/* More CPUID to match AMD better. #792*/
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msr = rdmsr(0x3009);
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msr.hi = 0x0C0C0A13D;
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msr.lo = 0x00000000;
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wrmsr(0x3009, msr);
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}
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/* cpubug 1398: enable MC if we KNOW we have DDR*/
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/* CPUbugIAENG1398
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*
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* ClearQuest #IAENG1398
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* The MC can not be enabled with SDR memory but can for DDR. Enable for
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* DDR here if the setup token is "Default"
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* Add this back to core by default once 2.0 CPUs are not supported.
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*/
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static void eng1398(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_GLCP+0x17);
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if ((msr.lo & 0xff) <= CPU_REV_2_0) {
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msr = rdmsr(GLCP_SYS_RSTPLL);
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if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
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return;
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}
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/* no CMOS/NVRAM to check, so enable MC Clock Gating */
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.lo |= 3; /* enable MC clock gating.*/
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wrmsr(MC_GLD_MSR_PM, msr);
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}
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/* CPUbugIAENG2900
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*
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* Clear Quest IAENG00002900, VSS 118.150
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*
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* BTB issue causes blue screen in windows, but the fix is required
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* for all operating systems.
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*/
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static void eng2900(void)
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{
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msr_t msr;
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printk(BIOS_DEBUG, "CPU_BUG:%s\n", __func__);
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/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
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msr = rdmsr(0x3003);
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msr.hi &= 0xFFFFF7FF;
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wrmsr(0x3003, msr);
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/* change this value to zero if you need to disable this BTB SWAPSiF. */
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if (1) {
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/* Disable enable_actions in DIAGCTL while setting up GLCP */
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msr.hi = 0;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x005f, msr);
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/* Changing DBGCLKCTL register to GeodeLink */
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msr.hi = 0;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x0016, msr);
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msr.hi = 0;
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msr.lo = 2;
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wrmsr(MSR_GLCP + 0x0016, msr);
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/* The code below sets up the CPU to stall for 4 GeodeLink
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* clocks when CPU is snooped. Because setting XSTATE to 0
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* overrides any other XSTATE action, the code will always
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* stall for 4 GeodeLink clocks after a snoop request goes
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* away even if it occured a clock or two later than a
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* different snoop; the stall signal will never 'glitch high'
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* for only one or two CPU clocks with this code.
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*/
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/* Send mb0 port 3 requests to upper GeodeLink diag bits
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[63:32] */
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msr.hi = 0;
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msr.lo = 0x80338041;
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wrmsr(MSR_GLIU0 + 0x2005, msr);
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/* set5m watches request ready from mb0 to CPU (snoop) */
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msr.hi = 0x5ad68000;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x0045, msr);
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/* SET4M will be high when state is idle (XSTATE=11) */
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msr.hi = 0;
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msr.lo = 0x0140;
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wrmsr(MSR_GLCP + 0x0044, msr);
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/* SET5n to watch for processor stalled state */
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msr.hi = 0x2000;
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msr.lo = 0;
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wrmsr(MSR_GLCP + 0x004D, msr);
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/* Writing action number 13: XSTATE=0 to occur when CPU is
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snooped unless we're stalled */
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msr.hi = 0;
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msr.lo = 0x00400000;
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wrmsr(MSR_GLCP + 0x0075, msr);
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/* Writing action number 11: inc XSTATE every GeodeLink clock
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unless we're idle */
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msr.hi = 0;
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msr.lo = 0x30000;
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wrmsr(MSR_GLCP + 0x0073, msr);
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/* Writing action number 5: STALL_CPU_PIPE when exitting idle
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state or not in idle state */
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msr.hi = 0;
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msr.lo = 0x00430000;
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wrmsr(MSR_GLCP + 0x006D, msr);
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/* Writing DIAGCTL Register to enable the stall action and to
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let set5m watch the upper GeodeLink diag bits. */
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msr.hi = 0;
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msr.lo = 0x80004000;
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wrmsr(MSR_GLCP + 0x005f, msr);
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}
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}
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static void bug118253(void)
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{
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/* GLPCI PIO Post Control shouldn't be enabled */
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msr_t msr;
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msr = rdmsr(GLPCI_SPARE);
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msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
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wrmsr(GLPCI_SPARE, msr);
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}
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static void bug118339(void)
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{
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/* per AMD, do this always */
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msr_t msr = {0,0};
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int msrnum;
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/* Disable enable_actions in DIAGCTL while setting up GLCP */
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wrmsr(MSR_GLCP + 0x005f, msr);
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/* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
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msrnum = MSR_GLCP + 0x042;
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/* msr.hi = 2d6b8000h */;
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msr.hi = 0x596b8000;
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msr.lo = 0x00000a00;
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wrmsr(msrnum, msr);
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/* SET3M fires if MBUS changed and VG pri is odd */
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msrnum = MSR_GLCP + 0x043;
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msr.hi = 0x596b8040;
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msr.lo = 0;
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wrmsr(msrnum, msr);
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/* Put VG request data on lower diag bus */
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msrnum = MSR_GLIU0 + 0x2005;
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msr.hi = 0;
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msr.lo = 0x80338041;
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wrmsr(msrnum, msr);
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/* Increment Y state if SET3M if true */
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msrnum = MSR_GLCP + 0x074;
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msr.hi = 0;
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msr.lo = 0x0000c000;
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wrmsr(msrnum, msr);
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/* Set up MBUS action to PRI=3 read of MBIU */
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msrnum = MSR_GLCP + 0x020;
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msr.hi = 0x0000d863;
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msr.lo = 0x20002000;
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wrmsr(msrnum, msr);
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/* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
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msrnum = MSR_GLCP + 0x071;
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msr.hi = 0;
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msr.lo = 0x00000c00;
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wrmsr(msrnum, msr);
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/* Writing DIAGCTL */
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msrnum = MSR_GLCP + 0x005f;
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msr.hi = 0;
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msr.lo = 0x80004000;
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wrmsr(msrnum, msr);
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/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
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* As per Todd Roberts in PBz1094 and PBz1095
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* Moved from CPUREG to CPUBUG per Tom Sylla
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*/
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msrnum = 0x04C000042; /* GLCP SETMCTL Register */
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msr = rdmsr(msrnum);
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msr.hi |= 8; /* Bit 35 = MCP_IN */
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wrmsr(msrnum, msr);
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}
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/* DisableMemoryReorder
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*
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* PBZ 3659:
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* The MC reordered transactions incorrectly and breaks coherency.
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* Disable reording and take a potential performance hit.
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* This is safe to do here and not in MC init since there is nothing
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* to maintain coherency with and the cache is not enabled yet.
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*/
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static void disablememoryreadorder(void)
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{
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msr_t msr;
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
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wrmsr(MC_CF8F_DATA, msr);
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}
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void cpubug(void)
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{
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msr_t msr;
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int rev;
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msr = rdmsr(GLCP_CHIP_REVID);
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rev = msr.lo & 0xff;
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if (rev < 0x20) {
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printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n", __func__);
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return;
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}
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printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);
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switch(rev)
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{
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case 0x20:
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pcideadlock();
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eng1398();
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/* cs 5530 bug; ignore
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bug752();
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*/
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break;
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case 0x21:
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pcideadlock();
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eng1398();
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eng2900();
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bug118339();
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break;
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case 0x22:
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case 0x30:
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break;
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default:
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printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
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return;
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}
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bug784();
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bug118253();
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disablememoryreadorder();
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printk(BIOS_DEBUG, "Done cpubug fixes \n");
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}
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