61b50a64bf
The board's PCIe port descriptors have the PCIe engine disabled, so update the devicetree accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
27 lines
683 B
Plaintext
27 lines
683 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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chip soc/amd/stoneyridge
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register "spd_addr_lookup" = "
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{
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{ {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
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}"
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device domain 0 on
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subsystemid 0x1022 0x1410 inherit
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device ref iommu on end
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device ref gfx on end
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device ref gfx_hda on end
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device ref gpp_bridge_0 on end # x4 PCIe slot
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device ref gpp_bridge_1 on end # M.2 slot
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device ref gpp_bridge_3 on end # x1 PCIe slot
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device ref gpp_bridge_4 on end # Cardreader
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device ref hda_bridge on end
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device ref hda on end
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device ref xhci on end
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device ref sata on end
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device ref ehci on end
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device ref sdhci on end
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end #domain
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end #chip soc/amd/stoneyridge
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