621aff9c02
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
46 lines
958 B
Plaintext
46 lines
958 B
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <baseboard/ec.h>
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#include <baseboard/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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// CPU
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/icelake/acpi/southbridge.asl>
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}
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}
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* ChromeOS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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