c6ef149a55
Change-Id: Ia0d6c952541cbd09d14e82336e6dc6d7d7d18b44 Signed-off-by: Tim Crawford <tcrawford@system76.com>
212 lines
7.6 KiB
Plaintext
212 lines
7.6 KiB
Plaintext
chip soc/intel/cannonlake
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register "common_soc_config" = "{
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# CPU (soc/intel/cannonlake/cpu.c)
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# Power limit
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register "power_limits_config" = "{
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.tdp_pl1_override = 45,
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.tdp_pl2_override = 90,
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}"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Misc
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register "AcousticNoiseMitigation" = "1"
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "4" # 4s
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "8"
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# Serial IRQ Continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "PMC_GPP_K"
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register "gpe0_dw1" = "PMC_GPP_G"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1558 0x65d1 inherit
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device pci 00.0 on end # Host Bridge
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device pci 01.0 on # GPU Port
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# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
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register "PcieClkSrcUsage[8]" = "0x40"
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register "PcieClkSrcClkReq[8]" = "8"
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chip drivers/gfx/nvidia
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device pci 00.0 on end # VGA controller
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device pci 00.1 on end # Audio device
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device pci 00.2 on end # USB xHCI Host controller
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device pci 00.3 on end # USB Type-C UCSI controller
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end
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end
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
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end
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device pci 14.2 on end # Shared SRAM
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device pci 14.3 on # CNVi wifi
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chip drivers/wifi/generic
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register "wake" = "PME_B0_EN_BIT"
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device generic 0 on end
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end
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end
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device pci 14.5 off end # SDCard
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device pci 15.0 on end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
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register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
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end
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1b.0 on # PCI Express Port 17
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# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
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register "PcieRpEnable[16]" = "1"
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register "PcieRpLtrEnable[16]" = "1"
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register "PcieRpHotPlug[16]" = "1"
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register "PcieClkSrcUsage[0]" = "16"
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register "PcieClkSrcClkReq[0]" = "0"
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end
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device pci 1b.1 off end # PCI Express Port 18
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device pci 1b.2 off end # PCI Express Port 19
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device pci 1b.3 off end # PCI Express Port 20
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device pci 1b.4 on # PCI Express Port 21
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# PCI Express root port #21 x4, Clock 10 (SSD2)
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieClkSrcUsage[10]" = "20"
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register "PcieClkSrcClkReq[10]" = "10"
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register "PcieRpSlotImplemented[20]" = "1"
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end
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device pci 1b.5 off end # PCI Express Port 22
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device pci 1b.6 off end # PCI Express Port 23
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device pci 1b.7 off end # PCI Express Port 24
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9
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# PCI Express root port #9 x4, Clock 9 (SSD1)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[9]" = "8"
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register "PcieClkSrcClkReq[9]" = "9"
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register "PcieRpSlotImplemented[8]" = "1"
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end
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 off end # PCI Express Port 13
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device pci 1d.5 on # PCI Express Port 14
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# PCI Express root port #14 x1, Clock 5 (GLAN)
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register "PcieRpEnable[13]" = "1"
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register "PcieRpLtrEnable[13]" = "1"
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register "PcieClkSrcUsage[5]" = "13"
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register "PcieClkSrcClkReq[5]" = "5"
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register "PcieRpSlotImplemented[13]" = "1"
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end
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device pci 1d.6 on # PCI Express Port 15
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# PCI Express root port #15 x1, Clock 7 (Card Reader)
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register "PcieRpEnable[14]" = "1"
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register "PcieRpLtrEnable[14]" = "1"
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register "PcieClkSrcUsage[7]" = "14"
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register "PcieClkSrcClkReq[7]" = "7"
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register "PcieRpSlotImplemented[14]" = "1"
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end
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device pci 1d.7 on # PCI Express Port 16
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# PCI Express root port #16 x1, Clock 6 (WLAN)
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register "PcieRpEnable[15]" = "1"
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register "PcieRpLtrEnable[15]" = "1"
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register "PcieClkSrcUsage[6]" = "15"
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register "PcieClkSrcClkReq[6]" = "6"
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register "PcieRpSlotImplemented[15]" = "1"
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end
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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register "gen1_dec" = "0x00040069"
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register "gen2_dec" = "0x00fc0e01"
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register "gen3_dec" = "0x00fc0f01"
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 off end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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register "PchHdaAudioLinkHda" = "1"
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end
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device pci 1f.4 on # SMBus
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chip drivers/i2c/tas5825m
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register "id" = "0"
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device i2c 4e on end # (8bit address: 0x9c)
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end
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end
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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