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Srinidhi N Kaushik d7b9e363e3 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163 
Update FSP headers for Tiger Lake platform generated based FSP
version 3163, which includes below additional UPDs:

FSPM:
TcssDma0En
TcssDma1En
FSPS:
PchFivrExtV1p05RailEnabledStates
PchFivrExtV1p05RailSupportedVoltageStates
PchFivrExtVnnRailEnabledStates
PchFivrExtVnnRailSupportedVoltageStates
PchFivrExtVnnRailSxVoltage
PchFivrExtV1p05RailIccMaximum
CstateLatencyControl5TimeUnit
VmdEnable

BUG=none
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icc893073629df59aef60162bed126d1f4b936e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41377
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:33:51 +00:00
..
amd
treewide: Remove "this file is part of" lines
2020-05-11 17:11:40 +00:00
cavium
treewide: Remove "this file is part of" lines
2020-05-11 17:11:40 +00:00
eltan
treewide: Remove "this file is part of" lines
2020-05-11 17:11:40 +00:00
google
treewide: Remove "this file is part of" lines
2020-05-11 17:11:40 +00:00
intel
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163
2020-05-18 07:33:51 +00:00
siemens
treewide: Remove "this file is part of" lines
2020-05-11 17:11:40 +00:00
Makefile.inc
vendorcode/eltan: Add vendor code for measured and verified boot
2019-06-04 10:41:53 +00:00