653d8717ba
Rename it and make it return an int, like other northbridges do. Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
143 lines
3.1 KiB
C
143 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <commonlib/helpers.h>
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <northbridge/intel/pineview/pineview.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm_reloc.h>
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#include <stdint.h>
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int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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*base = 0;
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*len = 0;
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const pci_devfn_t dev = HOST_BRIDGE;
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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u32 reg32;
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int max_buses;
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const struct {
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u16 num_buses;
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u32 addr_mask;
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} busmask[] = {
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{256, 0xf0000000},
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{128, 0xf8000000},
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{64, 0xfc000000},
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{0, 0},
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};
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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/* MMCFG not supported or not enabled */
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if (!(pciexbar_reg & (1 << 0))) {
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printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
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return 0;
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}
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reg32 = (pciexbar_reg >> 1) & 3;
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pciexbar = pciexbar_reg & busmask[reg32].addr_mask;
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max_buses = busmask[reg32].num_buses;
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if (!pciexbar) {
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printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
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return 0;
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}
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*base = pciexbar;
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*len = max_buses * MiB;
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return 1;
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}
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/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
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u32 decode_igd_memory_size(const u32 gms)
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{
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const u32 gmssize[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256};
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if (gms > 9) {
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printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n");
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return 0;
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}
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return gmssize[gms] << 10;
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}
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/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */
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u32 decode_igd_gtt_size(const u32 gsm)
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{
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const u8 gsmsize[] = {0, 1, 0, 0};
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if (gsm > 3) {
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printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n");
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return 0;
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}
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return (u32)(gsmsize[gsm] << 10);
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}
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/** Decodes used TSEG size to bytes. */
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static u32 decode_tseg_size(const u32 esmramc)
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{
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if (!(esmramc & 1))
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return 0;
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switch ((esmramc >> 1) & 3) {
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case 0:
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return 1 * MiB;
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case 1:
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return 2 * MiB;
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case 2:
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return 8 * MiB;
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case 3:
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default:
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die("Bad TSEG setting.\n");
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}
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}
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
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return decode_tseg_size(esmramc);
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}
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return pci_read_config32(HOST_BRIDGE, TSEG);
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}
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/*
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* Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment.
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* As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top_chipset(void)
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{
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return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/*
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* Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
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* CBMEM and the TSEG region.
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
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MTRR_TYPE_WRBACK);
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}
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