Files
system76-coreboot/src/mainboard/intel/adlrvp/Kconfig
Shelley Chen 6615c6eaf7 mrc_cache: Move code for triggering memory training into mrc_cache
Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.).  As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache.  The conditions are as follows:

  1.  If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
      switch is true)
  2.  If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
      means that memory training will occur after verified boot,
      meaning that mrc_cache will be filled with data from executing
      RW code.  So in this case, we never want to use the training
      data in the mrc_cache for recovery mode.
  3.  If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
      means that memory training happens before verfied boot, meaning
      that the mrc_cache data is generated by RO code, so it is safe
      to use for a recovery boot.
  4.  Any platform that does not use vboot should be unaffected.

Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode.  If the platform:
  1.  !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
  2.  HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set

BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
        ensure that memory retraining happens both times
        run dut-control power_state:rec twice on lazor
        ensure that memory retraining happens only first time
     2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
        boot twice to ensure caching of memory training occurred
	on each boot.

Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13 22:57:50 +00:00

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if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select DRIVERS_I2C_HID
select DRIVERS_I2C_GENERIC
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC
select DRIVERS_USB_ACPI
select DRIVERS_SPI_ACPI
select SOC_INTEL_ALDERLAKE
select HAVE_SPD_IN_CBFS
select DRIVERS_SOUNDWIRE_ALC711
config CHROMEOS
bool
default y
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
select GBB_FLAG_FORCE_MANUAL_RECOVERY
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
config MAINBOARD_DIR
string
default "intel/adlrvp"
config VARIANT_DIR
string
default "adlrvp_p" if BOARD_INTEL_ADLRVP_P
default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC
config GBB_HWID
string
depends on CHROMEOS
default "ADLRVPP"
config MAINBOARD_PART_NUMBER
string
default "adlrvp"
config MAINBOARD_FAMILY
string
default "Intel_adlrvp"
config OVERRIDE_DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config DIMM_SPD_SIZE
int
default 512
choice
prompt "ON BOARD EC"
default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P
default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC
help
This option allows you to select the on board EC to use.
Select whether the board has Intel EC or Chrome EC
config ADL_CHROME_EC
bool "Chrome EC"
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_ACPI
config ADL_INTEL_EC
bool "Intel EC"
select EC_ACPI
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
endchoice
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA
select HAS_RECOVERY_MRC_CACHE
config UART_FOR_CONSOLE
int
default 0
endif