Stefan Reinauer 6626d6a9e3 Add initial support for SMSC SIO1007 SuperI/O chip ...

early_serial and some ACPI needed for compilation

Change-Id: I5dd970676488697156e0630392884f31149ac85b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2012-04-06 21:23:08 +02:00

..

arch/x86

Fix support for RAM-less multi-processor init

2012-04-06 04:57:04 +02:00

boot

Add more timestamps in coreboot.

2012-03-30 17:45:20 +02:00

console

Add support to run SMM handler in TSEG instead of ASEG

2012-04-04 04:49:09 +02:00

cpu

Fixes and Sandybridge support for lapic cpu init

2012-04-06 18:47:01 +02:00

devices

x86, oprom: ensure DF is always cleared

2012-04-02 19:50:22 +02:00

drivers

Detect whether the OXPCIE card is really present while in the ROM stage.

2012-03-29 23:04:06 +02:00

ec

Add EC component for SMSC MEC1308/1310

2012-04-02 18:42:40 +02:00

include

Fixes and Sandybridge support for lapic cpu init

2012-04-06 18:47:01 +02:00

lib

Use fast memset in SMM mode, too

2012-04-04 19:45:10 +02:00

mainboard

S3 code whitespaces changes.

2012-04-02 21:11:54 +02:00

northbridge

amdfam10: add phenom II as known cpu

2012-04-05 23:12:24 +02:00

pc80

Move TPM code to romstage

2012-04-04 19:09:53 +02:00

southbridge

Add support for Intel Panther Point PCH

2012-04-04 19:10:51 +02:00

superio

Add initial support for SMSC SIO1007 SuperI/O chip

2012-04-06 21:23:08 +02:00

vendorcode

Don't unconditionally show ChromeOS options

2012-04-04 00:36:27 +02:00

Kconfig

Add support for Intel Panther Point PCH

2012-04-04 19:10:51 +02:00

Kconfig.deprecated_options

Unify ID_SECTION_OFFSET and mark it deprecated

2012-01-18 11:21:39 +01:00