662da6cf7b
Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
98 lines
4.4 KiB
Plaintext
98 lines
4.4 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/xeon_sp/skx
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# configure device interrupt routing
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register "ir00_routing" = "0x3210" # IR00, Dev31
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register "ir01_routing" = "0x3210" # IR01, Dev30
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register "ir02_routing" = "0x3210" # IR02, Dev29
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register "ir03_routing" = "0x3210" # IR03, Dev28
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register "ir04_routing" = "0x3210" # IR04, Dev27
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# configure interrupt polarity control
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register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
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register "ipc1" = "0x00000000" # IPC1
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register "ipc2" = "0x00000000" # IPC2
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register "ipc3" = "0x00000000" # IPC3
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# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
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# FB production turbo_ratio_limit is 0x1f1f1f2022222325
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register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
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# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
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register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
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# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
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register "pstate_req_ratio" = "0xa"
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# configure VTD
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register "vtd_support" = "1"
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register "coherency_support" = "1"
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register "ats_support" = "1"
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register "gen2_dec" = "0x000c0ca1" # IPMI KCS
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
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device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
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device pci 05.2 on end # Intel Corporation Device 2025
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device pci 05.4 on end # Intel Corporation Device 2026
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device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
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device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
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device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
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device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
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device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
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device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
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device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
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device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
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device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
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device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
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device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
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device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
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device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
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device pci 1f.0 on
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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register "bmc_i2c_address" = "0x20"
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register "bmc_boot_timeout" = "60"
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end
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end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
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device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
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device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
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device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
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end
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end
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