666c8f8fc5
Change-Id: Iefac6fd45791cf6a051450b41046f7e7ebc1dc41 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
60 lines
1.3 KiB
C
60 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbmem.h>
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#include <arch/io.h>
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#include <arch/romstage.h>
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#include <console/console.h>
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#include "memory.h"
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#include "fw_cfg.h"
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#define CMOS_ADDR_PORT 0x70
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#define CMOS_DATA_PORT 0x71
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#define HIGH_RAM_ADDR 0x35
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#define LOW_RAM_ADDR 0x34
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#define HIGH_HIGHRAM_ADDR 0x5d
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#define MID_HIGHRAM_ADDR 0x5c
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#define LOW_HIGHRAM_ADDR 0x5b
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unsigned long qemu_get_high_memory_size(void)
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{
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unsigned long high;
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outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT);
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high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22;
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outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT);
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high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
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outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT);
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high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
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return high;
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}
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unsigned long qemu_get_memory_size(void)
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{
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unsigned long tomk;
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outb(HIGH_RAM_ADDR, CMOS_ADDR_PORT);
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tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
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outb(LOW_RAM_ADDR, CMOS_ADDR_PORT);
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tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
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tomk += 16 * 1024;
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return tomk;
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}
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void *cbmem_top_chipset(void)
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{
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uintptr_t top = 0;
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top = fw_cfg_tolud();
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if (!top) {
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printk(BIOS_WARNING, "QEMU: Falling back to RAM info in CMOS\n");
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top = (uintptr_t)qemu_get_memory_size() * 1024;
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}
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return (void *)top;
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}
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/* Nothing to do, MTRRs are no-op on QEMU. */
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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}
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