6754dcda74
This replaces quark's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: I445c471b654abfa922b20215e52a2794529be120 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <soc/reg_access.h>
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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uintptr_t top_of_low_usable_memory;
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/* Locate the top of RAM */
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top_of_low_usable_memory = (uintptr_t) cbmem_top();
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top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
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/* Cache postcar and ramstage */
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postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
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MTRR_TYPE_WRBACK);
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/* Cache RMU area */
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postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
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0x10000, MTRR_TYPE_WRTHROUGH);
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/* Cache ESRAM */
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postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
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pcf->skip_common_mtrr = 1;
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/* Cache SPI flash - Write protect not supported */
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
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}
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