67633a558a
While most registers accesses don't need the use of the MCRX
register (upper 24 bits of address) the MCRX register should
be protected. The reference code could be doing accesses to
registers that initialized the MCRX register. Thus, any access
after that should ensure the MCRX register is initialized
appropriately.
BUG=None
BRANCH=None
TEST=Verified assembly output. Also, built and booted through
depthcharge.
Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <baytrail/iosf.h>
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#if !defined(__PRE_RAM__)
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#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
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static inline void write_iosf_reg(int reg, uint32_t value)
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{
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write32(IOSF_PCI_BASE + reg, value);
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}
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static inline uint32_t read_iosf_reg(int reg)
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{
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return read32(IOSF_PCI_BASE + reg);
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}
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#else
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static inline void write_iosf_reg(int reg, uint32_t value)
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{
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pci_write_config32(IOSF_PCI_DEV, reg, value);
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}
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static inline uint32_t read_iosf_reg(int reg)
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{
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return pci_read_config32(IOSF_PCI_DEV, reg);
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}
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#endif
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uint32_t iosf_bunit_read(int reg)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) |
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IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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return read_iosf_reg(MDR_REG);
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}
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void iosf_bunit_write(int reg, uint32_t val)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) |
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IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN;
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write_iosf_reg(MDR_REG, val);
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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}
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uint32_t iosf_dunit_read(int reg)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) |
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IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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return read_iosf_reg(MDR_REG);
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}
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uint32_t iosf_dunit_ch0_read(int reg)
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{
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return iosf_dunit_read(reg);
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}
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uint32_t iosf_dunit_ch1_read(int reg)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) |
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IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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return read_iosf_reg(MDR_REG);
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}
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void iosf_dunit_write(int reg, uint32_t val)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) |
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IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MDR_REG, val);
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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}
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uint32_t iosf_punit_read(int reg)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) |
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IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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return read_iosf_reg(MDR_REG);
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}
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void iosf_punit_write(int reg, uint32_t val)
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{
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uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) |
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IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) |
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IOSF_BYTE_EN;
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write_iosf_reg(MDR_REG, val);
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write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
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write_iosf_reg(MCR_REG, cr);
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}
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