This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
132 lines
4.0 KiB
Plaintext
132 lines
4.0 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-or-later
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chip northbridge/intel/sandybridge
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device domain 0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x1849 0x0100
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end
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device pci 01.0 on end # PEG - slot "PCIE1"
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device pci 02.0 on # iGPU
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subsystemid 0x1849 0x0102
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end
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chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
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register "gen1_dec" = "0x000c0291"
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register "gen2_dec" = "0x000c0241"
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register "gen3_dec" = "0x000c0251"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3f"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on # USB 3.0 Controller
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subsystemid 0x1849 0x1e31
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end
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x1849 0x1e3a
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end
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on # USB2 EHCI #2
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subsystemid 0x1849 0x1e2d
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end
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device pci 1b.0 on # High Definition Audio
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subsystemid 0x1849 0x8892
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end
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device pci 1c.0 on # PCIe Port #1 - slot "PCIE4", 4 lanes
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subsystemid 0x1849 0x1e10
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end
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 on # PCIe Port #5 - slot "PCIE2", 1 lane
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subsystemid 0x1849 0x1e18
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end
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device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE
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subsystemid 0x1849 0x1e1a
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end
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device pci 1c.6 on # PCIe Port #7 - slot "PCIE3", 1 lane
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subsystemid 0x1849 0x1e16
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end
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device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller
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subsystemid 0x1849 0x1e1e
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end
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device pci 1d.0 on # USB2 EHCI #1
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subsystemid 0x1849 0x1e26
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end
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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subsystemid 0x1849 0x1e4a
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chip superio/nuvoton/nct6776
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off end # COM2, IR
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GPIO8
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device pnp 2e.107 off end # GPIO9
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device pnp 2e.8 off end # WDT1
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device pnp 2e.108 off end # GPIO0
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device pnp 2e.208 off end # GPIOA
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device pnp 2e.308 on # GPIO base
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io 0x60 = 0x0
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irq 0xf0 = 0x3e # + GPIO1 direction
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irq 0xf1 = 0xde # + GPIO1 value
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end
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device pnp 2e.109 on end # GPIO1
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device pnp 2e.209 on # GPIO2
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irq 0xe0 = 0xff # + GPIO2 direction
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irq 0xe1 = 0x0c # + GPIO2 value
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end
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device pnp 2e.309 on # GPIO3
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irq 0xe4 = 0xf7 # + GPIO3 direction
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irq 0xe5 = 0x08 # + GPIO3 value
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end
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device pnp 2e.409 off end # GPIO4
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device pnp 2e.509 off end # GPIO5
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device pnp 2e.609 off end # GPIO6
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device pnp 2e.709 on end # GPIO7
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x10 # + enable 3VSBSW#
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irq 0xf0 = 0x20 # + pin 70 = 3VSBSW
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end
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device pnp 2e.b on # HWM, front panel LED
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irq 0x30 = 0xe1 # + Fan RPM sense pins
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io 0x60 = 0x0290 # + HWM base address
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end
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device pnp 2e.d off end # VID
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device pnp 2e.e off end # CIR WAKE-UP
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device pnp 2e.f off end # GPIO Push-Pull or Open-drain
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device pnp 2e.14 off end # SVID
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device pnp 2e.16 off end # Deep Sleep
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device pnp 2e.17 off end # GPIOA
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end
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end
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device pci 1f.2 on # SATA (AHCI)
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subsystemid 0x1849 0x1e02
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end
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device pci 1f.3 on # SMBus
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subsystemid 0x1849 0x1e22
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end
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device pci 1f.5 off end # SATA (Legacy)
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device pci 1f.6 off end # Thermal
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end
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end
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end
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